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Xilinx IP core USB2.0 Constraints


bdina77

Question

Hello All,

I am a little confused on how to constrain the USB2.0 from xilinx with my Arty z7 board.  I had a couple questions one more general the other specific:

1. (General) can you mix user created constraints with the ones that come with the board, i.e. the board package provided by the Digilent team.

2. I am getting errors saying there are unconstrained ports as well as unspecified I/O standard. I provided the contents of my constraints file for the project and can provide more files on request. I figured a) the project is too big to put up, and b) people don't want the project unless they need it. 

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set_property -dict { PACKAGE_PIN H16    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set

set_property -dict { PACKAGE_PIN D19    IOSTANDARD LVCMOS33 } [get_ports { reset_rtl }]; #IO_L4P_T0_35 Sch=BTN0


set_property IOSTANDARD LVCMOS18 [get_ports ULPI_0_data_io[0]]
set_property PACKAGE_PIN A14    [get_ports ULPI_0_data_io[0]]

set_property IOSTANDARD LVCMOS18 [get_ports ULPI_0_data_io[1]]
set_property PACKAGE_PIN D15    [get_ports ULPI_0_data_io[1]]

set_property IOSTANDARD LVCMOS18 [get_ports ULPI_0_data_io[2]]
set_property PACKAGE_PIN A12    [get_ports ULPI_0_data_io[2]]

set_property IOSTANDARD LVCMOS18 [get_ports ULPI_0_data_io[3]]
set_property PACKAGE_PIN F12    [get_ports ULPI_0_data_io[3]]

set_property IOSTANDARD LVCMOS18 [get_ports ULPI_0_data_io[4]]
set_property PACKAGE_PIN C16    [get_ports ULPI_0_data_io[4]]

set_property IOSTANDARD LVCMOS18 [get_ports ULPI_0_data_io[5]]
set_property PACKAGE_PIN A10    [get_ports ULPI_0_data_io[5]]

set_property IOSTANDARD LVCMOS18 [get_ports ULPI_0_data_io[6]]
set_property PACKAGE_PIN E13    [get_ports ULPI_0_data_io[6]]

set_property IOSTANDARD LVCMOS18 [get_ports ULPI_0_data_io[7]]
set_property PACKAGE_PIN C18    [get_ports ULPI_0_data_io[7]]


set_property IOSTANDARD LVCMOS18 [get_ports ULPI_0_dir]
set_property PACKAGE_PIN C13    [get_ports ULPI_0_dir]

set_property IOSTANDARD LVCMOS18 [get_ports ULPI_0_rst]
set_property PACKAGE_PIN D16    [get_ports ULPI_0_rst]

set_property IOSTANDARD LVCMOS18 [get_ports ULPI_0_next]
set_property PACKAGE_PIN E16    [get_ports ULPI_0_next]

# set the ULPI_clk constraints
create_clock -name ULPI_clk -period 16.667 [get_nets ULPI_0_clk]

set ulpi_input {ULPI_0_data_io, ULPI_0_dir,ULPI_0_next}
set ulpi_output {ULPI_0_data_io, ULPI_0_stop, ULPI_0_rst}

set_output_delay -max 7 -clock ULPI_0_clk $ulpi_output
set_input_delay -max 4.5 -clock ULPI_0_clk $ulpi_input
set_max_delay 24 -from [get_ports ULPI_0_dir] -to [get_ports ULPI_0_data_io[*]] -datapath_only

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I don't have the Arty Z7 board so I've not used the ULP TUSB1210 on it. I might have some helpful answers.

First of all the TUSBxxx On-the Go USB devices are almost always connected to the PS where drivers can handle the functionality that is missing in the device hardware. Looking at the schematic for your board this is the case for you too. There are no constraints for PS IO pins as the hardware is not in programmable logic ( the PL ) and can't be reconfigured.

For FPGA pin connected to programmable logic IO banks you can certainly append multiple constraints like location, IOSTANDARD, Drive Strength, etc onto one line. Usually, these get long enough so I've never tried appending timing constraints. Timing constraints can get messy all by themselves.

I prefer maintaining the constraints file myself rather than have Vivado or ISE do it and often have to add one that I don't know, or more likely can't remember,  the syntax for. There's a whole user manual for constraints that is isn't always helpful. It never hurts to start with the documentation but sometimes trying to get a specific answer is frustrating so I'm not shy about finding alternate means.

After place and route you can open the Implemented design and view the pin constraints in the I/O Planning view. From there you can select a new constraint or change a default one and let Vivado show you the syntax; just let Vivado ammend your existing constraints file. A similar process helps figure out timing constraint by using the Edit Timing Constraints tab or in the Timing Analysis View.

Sometimes, I have to work to figure out how to set reasonable timing constraints that result in consistently good designs with very low or 0 Timing scores.

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