Arty s7 25 - Running differential pairs?

[strathosphere]

Hello,

I am trying to implement LVDS (1.2V nominal) using the Digilent Arty-S7 25 board. The schematic shows that the JA and JB Pmod connectors have 4 diff. pairs per connector. However, it looks like VCCO (the power supply for this I/O bank) is tied to 3.3V. To my knowledge, there is no differential I/O protocol that uses 3.3V.

Does this mean that JA and JB can't be used for differential pairs? (Wouldn't that negate the point of running the differential pairs in the first place?)

Or do the pins just output the correct voltage when you implement the LVDS protocol?

Please help!

 

Thank you

[zygot]

On 9/12/2019 at 5:57 PM, strathosphere said:

To my knowledge, there is no differential I/O protocol that uses 3.3V.

Well you are partially correct. There certainly are differential logic standards for 3.3V logic. Decades ago 3.3V IO was the cutting edge and differential logic has preceded FPGAs by decades. But not since the Spartan 3A have any Xilinx devices that I can think of supported a differential IOSTANDARD for IO Banks powered by 3.3V Vcco. It is possible, though arguably not practical, to add termination allowing differential reception, in a board design.

The question is why would a company continue to put such connectors onto their boards, in the face of Xilinx documentation to the contrary, after having been called out by customers, without ever providing a PMOD designed to use it, basically wasting up to half of the IO pins provided on their development boards, when an suitable alternative is so trivial to implement. Why would an FPGA vendor put up with a partner subverting students and customers from learning how to use their devices in all of their glory? Why ponder questions that will never be answered? If you want to experiment with LVDS or differential IO on an FPGA find a board that is designed to let you do so. Finding such a board is a question for which there are answers.