Bitstream error - Zyb0_-z7-10- HDMI OUT

[tekson]

Dear all,

 

I tried to make a block design as per the zybo HDMI demo in vivado 2017.4 version. I m using zybo z7-10 While generating bit stream it is showing error something related to hdmi. 

here i m attaching the screen shot of error message . Can anyone please help me to figure out the error.

Thanks in advance

 

Regards,

Mebin 

 

[artvvb]

I believe that there is a bug in that particular version of the dvi2rgb decoder. A workaround would be to just set the TMDS clock range parameter to ">= 120 MHz".

Alternatively, you could replace the core in the project's repo folder with the latest version of that IP, which has resolved that bug, found in this ZIP.

Thanks,

Arthur

[artvvb]

Inclusion of the ps7_init and HDF file in the application project src folder (and the ps7_cortexa9_0 folder in the _today project) looks very strange to me. It also seems to have caused a lot of errors when I opened the workspace and built it on my system, so I am not sure if something strange happened when sharing the workspace.

If this reflects what you have on your system, you could try just creating a new Hello World application project to confirm that the exported hardware is valid, and that you can program and communicate with your board.

 <-- This is what I would expect the application project to look like. (Error is a result of using sources from another HDMI demo with differently-named IPs)

 

[tekson]

49 minutes ago, artvvb said:

Needed to double check.

Have you connected a serial terminal (Tera Term or whatever)? If so, what is being printed by the demo?

For what it's worth, I've seen similar projects halt on "printf" statements before, depending on Vivado version and the board used. xil_printf generally works fine, but does not accept floats. Here's a diff of a fix for that issue.

Could you zip and share your SDK workspace?

link:https://drive.google.com/open?id=1m0Foi2VJGceonyG8LFCa4gOeeVCHiELc

 

[artvvb]

Needed to double check.

Have you connected a serial terminal (Tera Term or whatever)? If so, what is being printed by the demo?

For what it's worth, I've seen similar projects halt on "printf" statements before, depending on Vivado version and the board used. xil_printf generally works fine, but does not accept floats. Here's a diff of a fix for that issue.

Could you zip and share your SDK workspace?

[tekson]

1 minute ago, artvvb said:

Have you programmed the hardware and run the demo application in Xilinx SDK? Both the hardware and software must be running on the board to get an image.

yes, i did

[artvvb]

Have you programmed the hardware and run the demo application in Xilinx SDK? Both the hardware and software must be running on the board to get an image.

[tekson]

15 minutes ago, artvvb said:

Looks like the board may be booting the out-of-box demo from QSPI flash. It is still possible to program it while this is happening, but you may still want to move the JP6 jumper to JTAG mode.

-Arthur

Hi, tried it by moving the jumper JP6 to jtag mode. But no signal in the display.

[artvvb]

Looks like the board may be booting the out-of-box demo from QSPI flash. It is still possible to program it while this is happening, but you may still want to move the JP6 jumper to JTAG mode.

-Arthur

[tekson]

8 hours ago, tekson said:

thanks for the reply 

but now i got error while implementation error.

error snapshot attached.

 

Hai,

bitstream generation is successfully completed when i add few lines of code in my previous xdc to the latest one you provided. And i got output on display. but i m not sure whether this is the correct one.

[tekson]

9 minutes ago, artvvb said:

This error is likely related to the rgb2dvi IP.

Please send a screenshot of its configuration (see below).

 

[artvvb]

This error is likely related to the rgb2dvi IP.

Please send a screenshot of its configuration (see below).

[tekson]

1 hour ago, artvvb said:

Looks like the project was just missing constraints. I am unsure what the root cause of the problem is, but I managed to generate a bitstream.

Download the attached XDC file and add it to your project.

 

Thanks,

Arthur

Zybo-Z7-Master.xdc 17.19 kB · 0 downloads

thanks for the reply 

but now i got error while implementation error.

error snapshot attached.

[artvvb]

Looks like the project was just missing constraints. I am unsure what the root cause of the problem is, but I managed to generate a bitstream.

Download the attached XDC file and add it to your project.

 

Thanks,

Arthur

Zybo-Z7-Master.xdc

[tekson]

18 hours ago, artvvb said:

Please use File -> Archive Project in Vivado to create a ZIP of the project. It should pick up dependencies outside of the project folder, in addition to the project folder itself.

Unfortunately, projects (particularly those using create_project style scripts) are not easily portable between different versions of Vivado. As stated in the HDMI demo's wiki page, Vivado 2016.4 must be used to run the create_project script.

The demo's release for 2018.2, found via the GitHub readme here, should at least be openable in any version of Vivado 2018.2 or newer, though problems may occur when not using that exact version.

Thanks,

Arthur

hi,

the link for the project attached

https://drive.google.com/open?id=1hlaMs-wpVEnfhxweX5hLNWDSwtAgCoI8

As i have only the licencse of vivado 2017.4, so I can't do it in 2018.2.

 

Thanks,

 

 

[artvvb]

Please use File -> Archive Project in Vivado to create a ZIP of the project. It should pick up dependencies outside of the project folder, in addition to the project folder itself.

Unfortunately, projects (particularly those using create_project style scripts) are not easily portable between different versions of Vivado. As stated in the HDMI demo's wiki page, Vivado 2016.4 must be used to run the create_project script.

The demo's release for 2018.2, found via the GitHub readme here, should at least be openable in any version of Vivado 2018.2 or newer, though problems may occur when not using that exact version.

Thanks,

Arthur

[tekson]

18 hours ago, artvvb said:

Hi @tekson

I believe that this issue may be related to capitalization of the port names in the constraint file. This is easily correctable by comparing the [get_ports <name>] names in the XDC file to the port map in the block design's *_wrapper.v file, and editing the names in the XDC to match the wrapper. Both files can be found in the Sources / Hierarchy pane in Vivado.

If you provide a link to the materials you are working from on our wiki or github, I should be able to correct the issue.

Thanks,

Arthur

HI,

 

Thanks for the support.

Here i m attaching the link of my project folder in vivado 2017.4.

https://drive.google.com/open?id=1qYPBff-duWx9FVwLuWtWumjfKbBOETFE

 

[artvvb]

Hi @tekson

I believe that this issue may be related to capitalization of the port names in the constraint file. This is easily correctable by comparing the [get_ports <name>] names in the XDC file to the port map in the block design's *_wrapper.v file, and editing the names in the XDC to match the wrapper. Both files can be found in the Sources / Hierarchy pane in Vivado.

If you provide a link to the materials you are working from on our wiki or github, I should be able to correct the issue.

Thanks,

Arthur