MYD-C7Z015 DAC Implementation

[immustafad]

Hello everybody,

I want to implement a dac example into my fpga board (MYD-C7Z015). My input will be 32 bit. First 4 bits are command bit which are C3=0, C2=0, C1=1, C0=1. Next 4 bits are Don't Care Bits. After Don't Care Bits, 12 Bits will be nothing(space). Then the rest 16 bits will be my data.In other words, I try to implement LTC-2601 to 32 bit input.

Now I have an IP with one output port. This Slave Ip has 4 registers. Also I use Zynq-7000 Processing System IP. In each rising edge of Zynq 7000 Processing System IP's clock I look at one bit and assign that bit to my slave register (in this example slv_reg0). Since my oscilloscope can measure up to 350 Mhz, I have to decrease the frequency of clock. That's why I just do this process in 20 rising edge of clock. In SDK part of my project, I just send some data to my slave register with Xil_Out32 function. However, after all this process the result is considerably different than I expected. My oscilloscope shows the only impulses. Also this part does not work properly. I expected a really nice square wave. But in the implementation it has some fluctuation in the wave. I leave my VHDL code below. Thank you.

port(
-- Users to add ports here
output : out std_logic := '0';
-- User ports ends
);

-- Add user logic here
-- S_AXI_ACLK is the clock from Zynq-7000 Processing System IP.
process(S_AXI_ACLK)
    variable index : integer := 0;
    variable counter: integer := 0;
    begin
        if rising_edge(S_AXI_ACLK) then
            case index is
                -- 4 Command Bits start
                when 0 =>
                    output <= '0';
                when 1 =>
                    output <= '0';
                when 2 =>
                    output <= '1';
                when 3 =>
                    output <= '1';
                -- 4 Command Bits end

                -- 4 Don't Care Bits start
                when 4 =>
                    output <= '0';
                when 5 =>
                    output <= '0';
                when 6 =>
                    output <= '0';
                when 7 =>
                    output <= '0';
                -- 4 Don't Care Bits end

                -- 16 Data Bits start
                when 8 =>
                   output <= slv_reg0(16);
                when 9 =>
                    output <= slv_reg0(17);
                when 10 =>
                    output <= slv_reg0(18);
                when 11 =>
                    output <= slv_reg0(19);
                when 12 =>
                    output <= slv_reg0(20);
                when 13 =>
                    output <= slv_reg0(21);
                when 14 =>
                    output <= slv_reg0(22);
                when 15 =>
                    output <= slv_reg0(23);
                when 16 =>
                    output <= slv_reg0(24);
                when 17 =>
                    output <= slv_reg0(25);
                when 18 =>
                    output <= slv_reg0(26);
                when 19 =>
                    output <= slv_reg0(27);
                when 20 =>
                    output <= slv_reg0(28);
                when 21 =>
                    output <= slv_reg0(29);
                when 22 =>
                    output <= slv_reg0(30);
                when 23 =>
                    output <= slv_reg0(31);
                -- Data Bits end
                when others =>

            end case;

            if counter = 0 then
                index := (index + 1) mod 24;
            end if;
            counter:= ( counter +1) mod 20;
    end if;
end process; 
-- User logic ends

Note: This vhdl code is from my axi peripheral ip. The rest of the ports, entity, logic and etc is created by the ip itself. So I did not put them here.

[artvvb]

Welcome to the forums!

Some comments:

You really should simulate this. Even a simple testbench could help you to start identifying potential issues.

How are you driving the chip select and serial clock? If the chip select is held low, it may cause the DAC to misinterpret data as 32-bit words, which could cause the DAC to discard the command bits, at least.

Because of the counter=0 check, index=0 only lasts for a single clock cycle.

Why hardcode the command bits? You have plenty of space left in your slave register.

 

Thanks,

Arthur

[xc6lx45]

just an observation: Most people would probably implement this around a shift register, instead of muxing a single bit.

Functionally it would be the same (of course, assuming timing is met).