hs3 fail to initialize

[amitceder]

hi

i baught 2 hs3 programmer and getting the same results.

trying to connect to a jtag supported ip i fail to initialize with adept latest gui.

i am able to enumarate.

i see input and output signals on chipscope of the jtag ports toggle according to a golden sequence.

the platform is xilinx ultrascale plus based and connected with jumper wires from the hs3 to pmod connector on the xilinx eval board.

at first i found a mirror in the hs3 pinout on digilent website.

once realized that the verf is corrected and all signals in chipscope appear as discussed above.

any ideas what can still fail the init of adept?

[JColvin]

Hi @amitceder,

The Digilent Adept software is not able to program the Xilinx UltraScale plus board. If you want to program the UltraScale board, you will need to you Xilinx's Vivado software with the JTAG HS3.

Let me know if you have any questions.

Thanks,
JColvin

[amitceder]

only a platform for the jtag supported ip.

of course i did not intend to program the fpga with it.

please read again and respond

 

[JColvin]

Hello @amitceder,

What platform are you attempting to use Adept and the JTAG HS3 with?

Thanks,
JColvin

[amitceder]

seems the gui was stuck on a jtag sampling loop.

after rebooting the pc it stopped and sampled correctly the ip as cpld unknown. 

platform is vcu118 and zcu104.

but it behave d the same prior to rebooting

[JColvin]

Hi @amitceder,

I don't quite know what you mean by it behaved the same prior to rebooting, but I confirmed with the design engineer who created Adept that Adept will not initialize on any UltraScale+ boards from Xilinx.

Let me know if you have any questions.

Thanks,
JColvin