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Arty A7, DMA from FPGA memory to DDR memory?



Dear Reader,

I need to move data from FPGA memory to DDR memory.  For other projects I have:
> DDR working with MicroBlaze, thanks for the help
  - (https://forum.digilentinc.com/topic/17948-place-30-172-sub-optimal-placement-for-a-clock-capable-io-pin-and-pll-pair/)
> Memory IP's (dualport and fifo) working from FPGA to AXI_GPIO to MicroBlaze

For a new project I need the copy from FPGA memory to DDR memory to be fast (48MB/sec).

I think:
(a) FPGA direct to DDR may work better, but from other posts it is difficult to setup and tune?
(b) If "DMA from IP memory to DDR memory" is possible:
      - Might it be fast enough?
      - Are there any example or clues?


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Hi @aadgl

DMA is fast enough. At least when there is little else using the DDR, Xilinx's AXI DMA IP can handle data rates significantly higher than your requirement (See the Performance section of its datasheet).

I've only built projects with the AXI DMA from scratch on Zynq devices before, which do not use the MIG, so I'm not certain how to go about connecting the MIG to the DMA. I believe that there is at least one demo for the Nexys Video that could be used as reference.

Getting it all set up for the first time can be tricky. If you have questions, we're happy to help. 

Some general thoughts:

Running all of the AXI/AXIS interfaces off of the same clock makes everything a lot easier.

Grouping your data into 32 bit words before streaming it to the DMA is also helpful.

Make sure that Microblaze and your IP are working on the same size of packet. The AXI DMA needs to be told by Microblaze how many words it is expecting, and the IP needs to provide a tlast signal at the expected time.

When trying to access DMA'd data from Microblaze, that data must be invalidated in the cache.

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Hi artvvb,

The Nexsys board looks nice.  The demo does drive a speaker, but wasn't the right starting point for my project.

I have since adapted from these examples:
> http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html
> https://www.xilinx.com/support/answers/57562.html
The first gets a Zynq block diagram setup and the second has the C code.

The second is referenced from this page that has three other examples, including interrupts.
> https://www.xilinx.com/support/answers/57550.html
These examples are good to get going, need significant work (including bug fixes), but do have enough working to get started.

A month later I have several Zynq versions of Stream/FIFO/SimpleDMA working, one running 250 MB/sec.  I have also adapted the Zynq work to Artix. Lots of twists and turns along the way, but doable.  Your "general thoughts" were helpful.


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