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RelativeHardware

Confusion on reset pins

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Hello everybody,

I have a little issue with a project i'm trying. I want to test writing some data with Matlab to the DDR memory on the arty-s7. I have tried connecting the gpio via axi to the jtag to axi and that worked great. Now i put the ddr memory in the design block diagram and it's not working like i expect. The error is weird that it's not connected to mig_7series_0/ui_clk_sync_rst but gives an error that there is a mismatch between them.

Does anybody see a mistake in my wiring and give me any pointers.

See the attached block diagram and the error. 1984344290_ARTYS7-blockdiagram.thumb.PNG.5ac435018e800cfc2ae9d0953cee1c4c.PNG

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Hi @RelativeHardware,

I'm not certain what the issue might be; is there a particular reason you are not using microblaze? I did attempt to create what you showed in your block design (though I don't have MATLAB to test this), though my block design ended up looking a bit different than yours; I attached an image of it below.. The messages I received while generating the bitstream was Vivado letting me know that the device_temp_i port was not connected to anything, but the bitstream was able to successfully generate.

Thanks,
JColvin

Arty DDR and mig.png

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