Nexys 4 DDR Ethernet Tutorial Query

[Luke Abela]

Good day,

I am currently attempting to set up an ethernet configuration on the Nexys 4 DDR FPGA and was doing so by following this link:

https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start

However, my issue arose with the Memory Interface Generator IP. The version of Vivado used for this tutorial was a 2015 edition, my edition is 2018.2. Since the 2015 edition, the run block automation option for the Memory interface generator IP is no longer available, and the page displayed below loads. I viewed the Xilinx tutorial on this generator, however, I have not been able to achieve the same pinouts as are displayed in the tutorial I was following. Could someone kindly advise a course of action?

Thank for your time,

Regards,

Luke Abela

 

[JColvin]

Hi @Luke Abela,

You would only receive that screen if you double clicked on the the MIG, which the tutorial you linked to does not instruct you to do. I just ran through the tutorial on Vivado 2018.2 and was able to generate the bitstream. Did you avoid clicking the "Run Connection Automation" on step 2.6? I was able to see the "Run Block Automation" for the mig_7series_0 block in step 4.1.

Thanks,
JColvin

[Luke Abela]

On ‎9‎/‎3‎/‎2019 at 11:59 PM, JColvin said:

Hi @Luke Abela,

You would only receive that screen if you double clicked on the the MIG, which the tutorial you linked to does not instruct you to do. I just ran through the tutorial on Vivado 2018.2 and was able to generate the bitstream. Did you avoid clicking the "Run Connection Automation" on step 2.6? I was able to see the "Run Block Automation" for the mig_7series_0 block in step 4.1.

Thanks,
JColvin

Hi JColvin, 

Thanks for the response, 

I ran through the tutorial and my issue is that block automation is not appearing when I input the Memory Interface Generator, hence why I clicked on it. Would you have any advice on this matter, alternatively is it essential to the setup of the echo server?

 

Regards,

Luke Abela

[JColvin]

Hi @Luke Abela,

My understanding is that the MIG is crucial for this particular tutorial, otherwise you would have to somehow configure the usage of DDR memory without an IP to handle the intracices for you, which is not a trivial task.

My recommendation (I'm not certain if you have already tried it) would be to close this project and Vivado and start with a fresh project. To confirm, you have the Digilent board files installed and are using Vivado 2018.2 on Windows 10?

Thanks,
JColvin

[Luke Abela]

Hello again,

 

Thank you for your assistance, I have now solved my issue. If you could kindly aid with me a final matter however, if you progress further along the tutorial, the tutorial states that you should be able to find a tab known as STDIO, this is unavailable for me on Xilinx SDK 2018.3

 

Could you kindly provide any information as to have to remedy this?

 

Thank you for your aid,

Luke 

 

[JColvin]

Hi @Luke Abela,

You only need to do that if you want to use the built in Xilinx SDK serial terminal. I would recommend using an external serial terminal such as tera term as is suggested in step 14 of the tutorial.

Thanks,
JColvin

[inconst]

Hi  @Luke Abela,
Can you explain how you solved this problem?

Regards,