bkzshabbaz Posted August 31, 2019 Share Posted August 31, 2019 Is there anything physically preventing me from putting the PHY on the Arty board in RMII mode? I'm generating a 50MHz eth ref clock using an MMCM , I'm driving the MII_MODE (G16) pin high to strap it to RMII. What else do I need to do? Link to comment Share on other sites More sharing options...
JColvin Posted September 5, 2019 Share Posted September 5, 2019 Hi @bkzshabbaz, I don't believe there is anything preventing you from doing this, though I would probably use the MII to RMII IP that Xilinx has available, much like this tutorial does for the Nexys 4 DDR. Naturally, you would need to change the xdc pin to match the ETH_REF_CLK to match the one for whichever Arty board you happen to be using. Let me know if you have any questions about this. Thanks, JColvin Link to comment Share on other sites More sharing options...
bkzshabbaz Posted September 13, 2019 Author Share Posted September 13, 2019 I think I have all the pin constraints correct. Unfortunately, my IP is RMII so that Xilinx MII to RMII IP won't work. I would need a RMII to MII IP. I guess I'll move forward with my application and see if it works. Link to comment Share on other sites More sharing options...
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bkzshabbaz
Is there anything physically preventing me from putting the PHY on the Arty board in RMII mode? I'm generating a 50MHz eth ref clock using an MMCM , I'm driving the MII_MODE (G16) pin high to strap it to RMII. What else do I need to do?
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