Custom AXI pheripheral

[chaitusvk]

i am a new bee creating simple axi adder   with help of the video but  i am getting module adder not able to found can any one help me

 

[jpeyron]

Hi @chaitusvk,

Are you adding the link to the IP core in " settings->ip->ip repository "? 

Please attach screen shots of your situation so that we can better assist you.

Here is a tutorial that might be helpful as well.   

best regards,

Jon

[chaitusvk]

On 8/30/2019 at 8:27 PM, jpeyron said:

Hi @chaitusvk,

Are you adding the link to the IP core in " settings->ip->ip repository "? 

Please attach screen shots of your situation so that we can better assist you.

Here is a tutorial that might be helpful as well.   

best regards,

Jon

Thank you very 

[chaitusvk]

@jpeyron

 

after checking file groups i am not getting synthesis error but i am not able to make SUM correctly sum is always zero 

even i create  axi peripheral with just led out from slv_reg0 ...i am unable to make it work...

i have attached the files ..it is created in VIvado 2019.1 please help me ...

 

at down i have attached ip core 

please check total source at https://github.com/chaitusvk/axi_peripheral

 

 

thank you very much @jpeyron

 

 

axi_adder.zip

[D@n]

@chaitusvk,

You haven't said what your problem was.  What is it your design does that makes you believe it doesn't work?

Dan

[chaitusvk]

12 minutes ago, D@n said:

@chaitusvk,

You haven't said what your problem was.  What is it your design does that makes you believe it doesn't work?

Dan

@D@n  just i am creating 8 bit adder 

 

i will write  A to one axi_slv_reg

and B to other reg

sum should be in third slv_reg

i am unable to create correct functinality...

thank you @D@n

 

 

[D@n]

@chaitusvk,

No, I got that much.  What values are you adding that are giving you the wrong answer?

When you add 1+1, you should get two, right?  When you add 7+7 you should get 14, right?  When you add 3+1 you should get 4.  Are you getting these answers?

Similarly when you add 0x53 + 1 you should get 84.  Is this the result you are getting?

Dan

[chaitusvk]

2 minutes ago, D@n said:

@chaitusvk,

No, I got that much.  What values are you adding that are giving you the wrong answer?

When you add 1+1, you should get two, right?  When you add 7+7 you should get 14, right?  When you add 3+1 you should get 4.  Are you getting these answers?

Similarly when you add 0x53 + 1 you should get 84.  Is this the result you are getting?

Dan

 I am always getting "0"  what ever the input put

there some mistake i am making ....i think so

 

[chaitusvk]

[D@n]

@chaitusvk,

Try reading back your adder inputs after writing them.

xil_printf("Inputs to adder: %08x\n", Xil_In32(XPAR_MYIP_ADDER_0_S00_AXI_BASEADDR));

What do you get there?

Dan

[chaitusvk]

Just now, D@n said:

@chaitusvk,

Try reading back your adder inputs after writing them.

xil_printf("Inputs to adder: %08x\n", Xil_In32(XPAR_MYIP_ADDER_0_S00_AXI_BASEADDR));

What do you get there?

Dan

@D@n Thank you for sending time dan i am getting what i am writing , 

 

two xil_prints i added first one giving me what i am writing second one giving blank 

i have create different ip like leds are given to lsb of reg_slv not nothing working ...

 

[D@n]

@chaitusvk,

Here's my puzzle --- while I see several (common) bugs in your core (Vivado's AXI-lite demo core has known bugs in it), bugs I'd like to discuss and share, I haven't yet found the bug causing the problem.

Let's try this ... set reg_data_out = -1 (independent of the axi_araddr), and let's just verify that you can read from your core in the first place.  I'm suspecting a couple of things, one possibility being that Vivado hasn't noticed you update the design with the adder, and so it's still building the older design.  (I think "run design automatiion" might help there ...)  Anotherr possibility is that you are accessing your core via the wrong address.  If you can set an LED from the core on any write (if (S_AXI_AWVALID && S_AXI_WVALID) led <= !led;) that would also help determine the same thing.

Dan

[chaitusvk]

On 9/2/2019 at 5:16 PM, D@n said:

@chaitusvk,

Here's my puzzle --- while I see several (common) bugs in your core (Vivado's AXI-lite demo core has known bugs in it), bugs I'd like to discuss and share, I haven't yet found the bug causing the problem.

Let's try this ... set reg_data_out = -1 (independent of the axi_araddr), and let's just verify that you can read from your core in the first place.  I'm suspecting a couple of things, one possibility being that Vivado hasn't noticed you update the design with the adder, and so it's still building the older design.  (I think "run design automatiion" might help there ...)  Anotherr possibility is that you are accessing your core via the wrong address.  If you can set an LED from the core on any write (if (S_AXI_AWVALID && S_AXI_WVALID) led <= !led;) that would also help determine the same thing.

Dan

@D@n Thank you very much Dan 

 

it is issue with linux system  ...i am using UBUNTU 16.04 and installed drivers by executing install drivers in data directory 

i tried the same example in Windows 7 but vivado 2016.1 it is working fine 

 

I have POST the bug in XLINX FORUM