Nexys 4 DDR Xilinx MIG Project: Pin/Bank Selection Mode

[George Onwubuya]

I am trying to setup DDR2 using the Xilinx Memory Interface Generator using Vivado 2017.2 for the Nexys 4 DDR board.

I am currently at the stage were I am prompted to select Pin/Bank Selection Mode: 

1. New design: Pick the optimum  banks for new design  

2. Fixed Pin Out: Pre-existing pinout is known or fixed 

 I am not sure what to choose. I have seen a lot of web forums that suggest using the second option and downloading the MIG ucf file. I tried this method but the Xilinx Memory Interface Generator in Vivado 2017.2 keeps crashing after I select the second option. 

Any assistance would be highly appreciated. 

[jpeyron]

Hi @George Onwubuya,

Welcome to the Digilent Forums!

Here is the Nexys 4 DDR's resource center.

Here is the SRAM to DDR Component resources that should be helpful. 

I would suggest using the Digilent board files and this older getting started with microblaze Nexys 4DDR tutorial that uses the DDR2 with microblaze.

best regards,

Jon

[George Onwubuya]

38 minutes ago, jpeyron said:

Hi @George Onwubuya,

Welcome to the Digilent Forums!

Here is the Nexys 4 DDR's resource center.

Here is the SRAM to DDR Component resources that should be helpful. 

I would suggest using the Digilent board files and this older getting started with microblaze Nexys 4DDR tutorial that uses the DDR2 with microblaze.

best regards,

Jon

I will take a look at the tutorial you recommended. Thanks