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Abhijit

PMOD VGA - can it work with Vivado 2019.1

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Hi,

Need some help in making the pmod vga work with Vivado IP Integrator. I am using version 2019.1. I am using Arty S7 50 board.

can someone please suggest how this can be made possible? 

Best regards,

Abhijit

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HI @jpeyron

Thank you for your suggestion. I was working on it yesterday and below is the update from my side.
1. I have created the project using create_project.tcl script in the PMOD package mentioned by you. The last compilation seems to be for vivado 2016.4 (I am on 2019.1). I have upgraded the XCI file for the clocking used in this code and repackaged the IP.  I have uncommented the code to enable resolution of 600x480 (disabled the 1920x1080@60Hz). The code has inbuilt HDL code to create box designs, however, what I need is ability to connect to an incoming video (image source). The current structure of this code does not seem to support this. Pl. suggest how should I approach this.

2. I tried rgb2vga IP as I thought it may also work in this context. Created the design and have attached for your review and suggestions. I have modified the output interfaces to suit RGB (3 down to 0). Bitstream generation is successful without any critical warning. I have attached the design and the TCL file for your review plea se.

3. Clock 2 output is 25 MHz. There is no display.

My apologies if this is going all over, but need your help to so that I can achieve the objective. The plan is to load image using ROM > process it > display on VGA.

Thank you for your time and help.

Best regards,

Abhijit

design.pdf design_1.tcl

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Hi @Abhijit,

Please attach your wrapper and xdc files for your current projects. Here is some non-digilent HDL tutorials here and here that show how to use the Pmod VGA with the Arty-A7. The tutorials cover displaying an image. 

best regards,

Jon

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Hi @jpeyron,

Did you get chance to look into this? It will help if you could spare some time.

thanks and best regards,

Abhijit

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Hi @Abhijit

Your block design appears to be on the right track, but the AXI VDMA requires extensive configuration via it's S_AXI_LITE interface. Controlling the AXI interface requires a microblaze processor to accomplish. If you haven't used Microblaze before, the Getting Started With IPI guide would probably be a good place to start.

We have a few example designs for video applications using a similar approach to what you have started, but these typically target HDMI ports and use Zynq-based boards (example). It should be possible to get one of these designs fit what you need by replacing the Zynq processor with a Microblaze processor, replacing the rgb2dvi IP with the rgb2vga, and altering the Xilinx SDK sources to support Microblaze. Fair warning though, creating these video applications has a pretty steep learning curve.

Thanks,

Arthur

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Thank you so much @artvvb

Really appreciate you looking into this. I think it might be a good idea for me to get the TPG working with rest of the blocks, before I move onto more complex design. I will prefer not to take SDK route (is it inevitable / necessary for microblaze based design?) 

thank you so much for your time.

best regards,

Abhijit

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Microblaze (or some other soft processor) is almost totally necessary to configure many of Xilinx's IPs. While it's possible to create an AXI master, the interface is complex, and the IP drivers provided in SDK are a big help.

Thanks,

Arthur

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