Accessing FPGA (logic) data through the UART

[RFtmi]

The Zynq FPGA that I am looking at for an application has a processor unit and a programmable logic unit. I know how you can write a HDL code to use the logic part. For the processor part it seems that I need to use the IP integrator to get the CPU, peripherals, and interface properly configured and then generate the HDL code for it. In the generated HDL code, "HDL wrapper", the blocks are defined as modules. Then I need to use SDK to program the bit stream and program a C code for the processor (for example). 

My question is, if I want to have a logic (let's say an 8 bit counter) on the logic part, and then the processor and the XADC that is controlled by the processor, how can I access the output of the 8-bit counter via processors and transfer it to the PC through the USB UART port? Do I need to define another top level HDL file and instantiate the HDL wrapper plus my 8-bit counter code? 

My question is sort of general for now, so any example or comment would be helpful.

[jpeyron]

Hi @RFtmi,

You can add the HDL using the add a module function on the block design and connect the output to the input of an AXI-GPIO IP Core. Here is a forum thread that discusses doing this with another 

best regards,

Jon