I am really enjoying my Basys3. I already VHDL coded/simulated/tested a little SPI and a little I2S controller (connected to a AdaFruit DAC, but i will try/compare it with the I2S2 soon).
Thanks to many threads on this forum (double flop...), clock domains were not such a big problem
I am designing a formant/phase modulation synthesizer.
It will be based on 1024 "operators" (oscillators with phase modulation, phase hard sync and many other delicacies).
I use a dual port BRAM connected to a SPI controller for input parameters (frequencies and gains) and another set of BRAM for state variables (for example the phase of each operator).
I am designing the "operator" processor as a pipeline (so that it will calculate the equivalent of 1024 oscillators at the I2S 96kHz sample rate).
I'd like to have a rule of thumb for the granularity of the pipeline for a targeted clock frequency.
(for example the number of adders or multiplexers between two pipeline registers at 100MHz or 200MHz)
I browsed many documents and i did not find such a rule of thumb... thus i have a tendency to over-pipeline my design... and it makes it quite confusing.
Is there some Xilinx document that gives some advice/good practice ?
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SmashedTransistors
Hello,
I am really enjoying my Basys3. I already VHDL coded/simulated/tested a little SPI and a little I2S controller (connected to a AdaFruit DAC, but i will try/compare it with the I2S2 soon).
Thanks to many threads on this forum (double flop...), clock domains were not such a big problem
I am designing a formant/phase modulation synthesizer.
It will be based on 1024 "operators" (oscillators with phase modulation, phase hard sync and many other delicacies).
I use a dual port BRAM connected to a SPI controller for input parameters (frequencies and gains) and another set of BRAM for state variables (for example the phase of each operator).
I am designing the "operator" processor as a pipeline (so that it will calculate the equivalent of 1024 oscillators at the I2S 96kHz sample rate).
I'd like to have a rule of thumb for the granularity of the pipeline for a targeted clock frequency.
(for example the number of adders or multiplexers between two pipeline registers at 100MHz or 200MHz)
I browsed many documents and i did not find such a rule of thumb... thus i have a tendency to over-pipeline my design... and it makes it quite confusing.
Is there some Xilinx document that gives some advice/good practice ?
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