how to instantiate a verilog module in a VHDL project?

[helic]

I'm trying to put my own verilog module into official nexys video hdmi demo, but vivado 2016.4 keeps telling me "missing design sources" and reports error for implementation.

I did as Xilinx says, declared a VHDL component then used named association to instantiate, is it better to declare an entity?

EDIT:

Verilog module(originally a testbench for another project):

module testoverlay_0(
                input wire                 rst_n,
                input wire                 clk,
                
                output reg[23:0]      RGBOut,
                output reg                HSync1,
                output reg                VSync1
);

 

VHDL:

  component testoverlay_0 is
    port (
        rst_n: in STD_LOGIC;
        clk: in STD_LOGIC;
        RGBOut: out STD_LOGIC_VECTOR ( 23 downto 0 );
        HSync1: out STD_LOGIC;
        VSync1: out STD_LOGIC
);
end component testoverlay_0;

test_overlay: component testoverlay_0
    port map (
        rst_n    => reset_1,
        clk        => sys_clk_i_1,
        RGBOut(23 downto 0)    =>  v_axi4s_vid_out_0_vid_io_out_DATA_1(23 downto 0),
        HSync1    =>  v_axi4s_vid_out_0_vid_io_out_HSYNC_1,
        VSync1    =>  v_axi4s_vid_out_0_vid_io_out_VSYNC_1
    );

[hamster]

I've done it before without issue, and all I can suggest is that you look carefully at your component/module names and especially uppercase / lowercase.

Maybe add some code snippets to the thread?

 

[helic]

1 hour ago, hamster said:

I've done it before without issue, and all I can suggest is that you look carefully at your component/module names and especially uppercase / lowercase.

Maybe add some code snippets to the thread?

 

i checked at very first and found no spelling mistake, so it's confusing now.

and here are the codes.

[hamster]

Maybe remove the 'reg' from the Verilog port definition? 

[helic]

@hamster, thanks for reply and problem solved, yet in another way

The vhdl file is in a block design, so vivado cannot identify my verilog module directly. I'm doing package works now.

 

[zygot]

4 hours ago, helic said:

problem solved, yet in another way

It would probably be more useful for you to know why you were having issues. As you found out, it is possible to create a Verilog module that can't be instantiated in VHDL. Specifically, try declaring your module port IO without wire or register assignments. I know, it involves more writing as you'll have to add wire and reg assignments anyway. There is no std_logic_vector equivalent in VHDL for the Verilog reg. I supposed that you get points for finding a work-around but then you also get deductions for claiming that you've solved your problem...

Friendly advise. Instead of seeing issues as obstacles to be avoided see them as opportunities for experimentation and learning. You'll be much more productive and happier in the long run.