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Uploading a bitstream and running an application from Flash memory

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Dear all,

I'm using Vivado 2018.3 and a Zybo Z7010 board.

I have finally finished my project (I actually owe this forum much), and I am now trying to use the board without having to open nor Vivado neither the SDK.

Basically, I know that I can program the QSPI flash memory of the board so that the program can run without having to upload it. How this works is still unclear, is switching from JTAG to QSPI enough or should I do something on Vivado?

However, I am also using the Zynq processor which runs an application that I start from the SDK. Can I avoid opening the SDK?

The better thing would be if I could programm the FPGA through Matlab but I don't know if this is possible.

Could you point me to some tutorials or the matlab functions (if they exist...).

Thank you very much,


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when you load a Zynq bitstream from Vivado there are a few things that happen "automagically", like powering up the level shifters on the PS-PL interface (clock!). Zynq doesn't support FPGA-only operation, but you can manage with an autogenerated "FSBL" (first stage boot loader).

Vivado, "export hardware" and include bitstream checked.

Then you need to open SDK ("File/launch SDK") and create a "FSBL" project. Compiling it results in a .elf file. Put this into a boot image (.bin or .mcs) at the first position, the FPGA bitstream on position 2. Flash the result and the FPGA image will load at powerup when QSPI mode is jumpered.

Note, the SDK flash utility does not work reliably (sometimes fails with error) when Vivado is still connected to the hardware.

I'm sure there are tutorials but this as a two-line answer.



Edited by xc6lx45
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Hi @NotMyCupOfTea,

We have an old ZedBoard programming tutorial. This was not checked for a while so might contain errors. Also, it's made for older versions of Vivado SDK. Things might be a bit different with the current versions. It goes through the steps @xc6lx45 mentioned above. I hope it helps.



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