Microblaze on Arty Tutorial

[rlramirez77]

Following the Digilent tutorial to get the Microblaze built on an Arty board, I had no problems until Step 7 where you generate the  bitstream. When I try to do this, it kicks off validation and reports no errors, but sits for many minutes (I waited up to 45) doing nothing on the supposed build of the bitstream. The cpu utilization on my PC falls to a few %. I believe I am using the 2015.4 update of Vivado.

Any suggestions?

[JColvin]

Hi rlramirez77,

I have asked some of our applications engineers about this; they'll get back to you here on the Forum.

Thanks,
JColvin

[rlramirez77]

Maybe this will help too - I have included a screen grab of a portion of the Vivado License Manager screen. I previously also purchased a BASYS3 board and perhaps this is why the shot shows the license for Vivado HLS expiring 4/26, but as that date has not passed yet, it might just be a coincidence.

 

Russ

 

[AndrewHolzer]

Hi rlramirez77,

Could you please give your computer specs and the Vivado TCL output when you are generate bitstream? It might also be possible that your computer is hanging up in the synthesis stage of the design flow. If you generate bitstream without synthesizing and implementing your design, the tools will go through those steps before actually generating the bitstream. At the same time, synthesizing a Microblaze project takes some time and is dependent on your specs. 

We'll help you get to the bottom of this,
Andrew

[rlramirez77]

Hello Andrew, I was able to get through synthesis in that Vivado showed the task completed before moving on to the creation of the bitstream. The synthesis step took about 20 mins to complete. This was done on Vivado 2015.4, but I have since applied the update to 2015.4.2. I am on a laptop with 16GB of RAM and (4) A8-3500M cores, with Win 7 Pro x64. I have not attempted this again since moving up to 2015.4.2 due to time constraints. Thanks.

 

Russ

[rlramirez77]

Andrew, here is the Tcl console upon opening this project now:

start_gui
open_project C:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.xpr
open_project C:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'.
WARNING: [BD 41-1661] One or more IPs have been locked in the design 'system.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
system_axi_uartlite_0_0

Is the system_axi_uartlite_0_0 locked IP an issue? The report_IP_status recommends an upgrade of this IP and only this 1 source. If you want me to re-run the project and capture one of these logs, let me know.

The Message log is as follows:

Vivado Commandsopen_project C:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.xpr
[IP_Flow 19-234] Refreshing IP repositories
[IP_Flow 19-1704] No user IP repositories specified
[IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'.
[BD 41-1661] One or more IPs have been locked in the design 'system.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
system_axi_uartlite_0_0

Analysis Resultssim_1[HDL 9-2216] Analyzing Verilog file "C:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/hdl/system_wrapper.v" into library work ["C:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/hdl/system_wrapper.v":1]
sources_1[HDL 9-1061] Parsing VHDL file "c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/address_decoder.vhd" into library axi_lite_ipif_v3_0_3 ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/address_decoder.vhd":1]
Synthesis[IP_Flow 19-234] Refreshing IP repositories
[IP_Flow 19-1704] No user IP repositories specified
[IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'.
[Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35ti'
[Synth 8-638] synthesizing module 'system_wrapper' ["C:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/hdl/system_wrapper.v":12]
[Synth 8-256] done synthesizing module 'm00_couplers_imp_1TEAG88' (1#1) ["C:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/hdl/system.v":12]
[Synth 8-350] instance 'auto_us' of module 'system_auto_us_0' requires 72 connections, but only 70 given ["C:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/hdl/system.v":929]
[Synth 8-155] case statement is not full and has no default ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_reg_srl_fifo.v":157]
[Synth 8-689] width (1) of port connection 's_axi_awready' does not match port width (2) of module 'system_xbar_0' ["C:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/hdl/system.v":2483]
[Synth 8-5534] Detected attribute (* max_fanout = "10000" *) ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_uartlite_v2_0/hdl/src/vhdl/axi_uartlite.vhd":169]
[Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd":514]
[Synth 8-3491] module 'axi_uartlite' declared at 'c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_uartlite_v2_0/hdl/src/vhdl/axi_uartlite.vhd:150' bound to instance 'U0' of component 'axi_uartlite' ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ip/system_axi_uartlite_0_0/synth/system_axi_uartlite_0_0.vhd":156]
[Synth 8-115] binding instance 'i_0' in module 'PC_Module_gti' to reference 'keep__34' which has no pins
[Synth 8-226] default block is never used ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/slave_attachment.vhd":448]
[Synth 8-312] ignoring unsynthesizable construct: assertion statement ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/microblaze_v9_5/hdl/microblaze_v9_5_vh_rfs.vhd":55038]
[Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
[Synth 8-3936] Found unconnected internal register 'gen_arbiter.next_rr_hot_reg' and it is trimmed from '16' to '2' bits. ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_addr_arbiter.v":276]
[Synth 8-3919] null assignment ignored ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_uartlite_v2_0/hdl/src/vhdl/uartlite_core.vhd":428]
[Synth 8-3848] Net ui_addn_clk_0 in module/entity mig_7series_v2_4_infrastructure does not have driver. ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v2_4_infrastructure.v":138]
[Synth 8-4471] merging register 'WB_Div_Overflow_reg' into 'ex_start_div_i_reg' ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/microblaze_v9_5/hdl/microblaze_v9_5_vh_rfs.vhd":45297]
[Synth 8-3536] HDL ADVISOR - Pragma parallel_case detected. Simulation mismatch may occur ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/phy/mig_7series_v2_4_ddr_phy_init.v":1956]
[Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/axi/mig_7series_v2_4_axi_mc_r_channel.v":189]
[Synth 8-3295] tying undriven pin ddr_byte_group_io:iserdes_clk to constant 0 ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/phy/mig_7series_v2_4_ddr_byte_lane.v":630]
[Device 21-403] Loading part xc7a35ticsg324-1L
[Project 1-236] Implementation specific constraints were found while reading constraint file [c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in ['Undefined'] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
[Timing 38-2] Deriving generated clocks ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ip/system_mdm_1_0/system_mdm_1_0.xdc":50]
[Synth 8-5546] ROM "read_cs" won't be mapped to RAM because it is too sparse
[Synth 8-3537] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the inputs of the operator ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_command_fifo.v":275]
[Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_data_fifo_v2_1_6_axic_reg_srl_fifo'
[Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
[Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v2_4_ddr_phy_tempmon'
[Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_data_fifo_v2_1_6_axic_reg_srl_fifo'
[Synth 8-3538] Detected potentially large (wide) register LOCKSTEP_Out_reg ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ipshared/xilinx.com/microblaze_v9_5/hdl/microblaze_v9_5_vh_rfs.vhd":92382]
[Synth 8-3332] Sequential element (\bank_mach0/arb_mux0/arb_row_col0/sent_col_lcl_r_reg ) is unused and will be removed from module mig_7series_v2_4_mc.
[Synth 8-3886] merging instance 'system_i/mig_7series_0/\u_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0 /\bank_mach0/bank_cntrl[0].bank0/bank_state0/phy_mc_ctl_full_r_reg ' (FDR) to 'system_i/mig_7series_0/\u_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0 /\bank_mach0/bank_cntrl[1].bank0/bank_state0/phy_mc_ctl_full_r_reg '
[Synth 8-3333] propagating constant 0 across sequential element (system_i/mig_7series_0/\u_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0 /\rank_mach0/rank_common0/periodic_read_request.periodic_rd_rank_r_lcl_reg[0] )
[Synth 8-3321] Empty through list for constraint at line 342 of c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/constraints/system_mig_7series_0_0.xdc. ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/constraints/system_mig_7series_0_0.xdc":342]
[Synth 8-5365] Flop u_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0] is being inverted and renamed to u_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv.
[Synth 8-4618] Found max_fanout attribute set to 40 on net \u_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty [4]. Fanout reduced from 64 to 32 by creating 1 replicas.
[Synth 8-5396] Clock pin CLKIN1 has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net ["c:/Users/ramirez/vivado/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v2_4_infrastructure.v":301]
[Project 1-571] Translating synthesized netlist
[Netlist 29-17] Analyzing 741 Unisim elements for replacement
[Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
[Project 1-570] Preparing netlist for logic optimization
[Opt 31-138] Pushed 4 inverter(s) to 28 load pin(s).
[Project 1-111] Unisim Transformation Summary:
  A total of 587 instances were transformed.
  FDC_1 => FDCE (inverted pins: C): 1 instances
  FDE => FDRE: 32 instances
  FDR => FDRE: 176 instances
  FDRE_1 => FDRE (inverted pins: C): 1 instances
  FDS => FDSE: 3 instances
  IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT, IBUFDS_INTERMDISABLE_INT, OBUFTDS, OBUFTDS, INV): 2 instances
  IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances
  LUT6_2 => LUT6_2 (LUT6, LUT5): 80 instances
  MULT_AND => LUT2: 1 instances
  MUXCY_L => MUXCY: 174 instances
  OBUFDS => OBUFDS_DUAL_BUF (OBUFDS, OBUFDS, INV): 1 instances
  RAM32M => RAM32M (RAMS32, RAMS32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32): 67 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
  SRL16 => SRL16E: 1 instances

[Common 17-83] Releasing license: Synthesis
[Common 17-206] Exiting Vivado at Sun Mar 27 17:38:18 2016...
 

[rlramirez77]

UPDATE: I re-ran the Implementation and it worked fine this time, completing in about 9:40. I then ran the Generate Bitstream and moved on to Steps 8.1 and 8.2. It turned-out that I did not have the SDK installed for some reason, but am doing that now as I write this.

[rlramirez77]

..and just like that, I reached Hello World in PuTTY.

This question can be considered answered or closed. Thanks.

Russ

[AndrewHolzer]

I'm glad you were able to complete the tutorial project! Have fun with your Arty!

Andrew