chaitusvk Posted August 15, 2019 Share Posted August 15, 2019 I want to generate the signal as shown below , i have pwm wave and sine wave generated(12 bit from DDS compiler) please guide how i can generate the Amplitude modulated wave from that DDS compiler dont have option for amplitude setting thanks you Link to comment Share on other sites More sharing options...
xc6lx45 Posted August 15, 2019 Share Posted August 15, 2019 You could use the multiplication operator "*" in Verilog (similar VHDL). For example, scale the "mark" sections (level 10) by 1024, the "space" sections (level 3) by 307. This will increase the bit width from 12 to 22 bits, therefore discard the lowest 10 bits and you are back at 12 bits. Pay attention to "signed" signals at input and output, otherwise the result will be garbled. Link to comment Share on other sites More sharing options...
D@n Posted August 15, 2019 Share Posted August 15, 2019 The carrier phase alignment question is pretty important. What carrier frequency is this thing supposed to be operating at? And ... is it in the range of what an FPGA can create? Dan Link to comment Share on other sites More sharing options...
chaitusvk Posted August 15, 2019 Author Share Posted August 15, 2019 6 minutes ago, D@n said: The carrier phase alignment question is pretty important. What carrier frequency is this thing supposed to be operating at? And ... is it in the range of what an FPGA can create? Dan 1 khz is carrier frequency .... i will be using zyboz7 board and each symbol takes 10 ms Link to comment Share on other sites More sharing options...
chaitusvk Posted August 15, 2019 Author Share Posted August 15, 2019 8 hours ago, D@n said: The carrier phase alignment question is pretty important. What carrier frequency is this thing supposed to be operating at? And ... is it in the range of what an FPGA can create? Dan @D@n Can you please help how to do carrier phase alignment ..please clock driving DDS and producing PWN is same in my design Link to comment Share on other sites More sharing options...
D@n Posted August 16, 2019 Share Posted August 16, 2019 @chaitusvk, I notice that the on and off periods are ... not on an obvious integer spacing. Is there some greatest common sublength that all of the bits are described with? Is the carrier a multiple of this subwidth? Your goal is to create this signal, right? I think my goal would follow @xc6lx45's approach: create some form of NCO for the carrier, and then use multiples of it (if possible) for handling bit periods. You might find this article, or even this one, valuable back-reading on the topic. Dan Link to comment Share on other sites More sharing options...
chaitusvk Posted August 19, 2019 Author Share Posted August 19, 2019 On 8/16/2019 at 7:33 AM, D@n said: @chaitusvk, I notice that the on and off periods are ... not on an obvious integer spacing. Is there some greatest common sublength that all of the bits are described with? Is the carrier a multiple of this subwidth? Your goal is to create this signal, right? I think my goal would follow @xc6lx45's approach: create some form of NCO for the carrier, and then use multiples of it (if possible) for handling bit periods. You might find this article, or even this one, valuable back-reading on the topic. Dan thank you @D@n what i am creating is IRIG-B am signal ,it has three digital symbols " MARK " , " 1 " , " 0 " MARK or Reference is defined by square pulse : 8msec high 2 msec low 80% duty cycle 1 is defined by : 5msec high 5 msec low 0 is defined by : 2 msec high 8 msec low Every symbol start with HIGH state Link to comment Share on other sites More sharing options...
chaitusvk Posted August 19, 2019 Author Share Posted August 19, 2019 @D@n i have another question How to generate 1khz square which is synchronous to 1pps ie both posedges has to be at same time 1pps: from GPS reciver i have 10mhz from Rb Atomic clock I tried Resetting decade counters with 1pps to achieve sync but it around 200 ns i need even less around 50 ns please help me i am designing IRIG-B code from GPS module with FPGA Link to comment Share on other sites More sharing options...
D@n Posted August 19, 2019 Share Posted August 19, 2019 @chaitusvk, You might find the GPS integration to be a bit of a challenge. It's doable, but it will be a bit of a challenge. I was able to synchronize my Arty A7 board to within about 250ns or so of true GPS time. as reported by the PMod GPS. Suppose we try this: Generate a 32-bit counter (could be more bits, could be less), and increment it so that it rolls over 1000 times a second. (Don't count from 0 to any number other than 2^(N-1)--it'll make the next step harder) Also, generate a second signal that is one every time the clock is about to roll over. (Might be easier to delay the counter by one, and then use: { o_stb, counter } <= counter + increment; together with o_counter <= counter) Use the top N bits of the counter in your counter to generate a sine wave via either a cordic or a table lookup. If using a cordic, use the o_stb value from earlier to enable a logic circuit that selects between two magnitude values, using them as input to the CORDIC If you are just using a table lookup, then multiply the output of the lookup by the same magnitude value That should get you pretty close, no? Now, if I wanted GPS synchronization, I'd start with a core I'd written for that purpose. This core keeps track of the timing since the top of a GPS second in a 2^32 bit counter. If you multiply that counter by 1000 rather than adding the increment to it as we did above, then you should have a 1kHz tone synchronized to GPS. Dan Link to comment Share on other sites More sharing options...
chaitusvk Posted August 19, 2019 Author Share Posted August 19, 2019 8 minutes ago, D@n said: @chaitusvk, You might find the GPS integration to be a bit of a challenge. It's doable, but it will be a bit of a challenge. I was able to synchronize my Arty A7 board to within about 250ns or so of true GPS time. as reported by the PMod GPS. Suppose we try this: Generate a 32-bit counter (could be more bits, could be less), and increment it so that it rolls over 1000 times a second. (Don't count from 0 to any number other than 2^(N-1)--it'll make the next step harder) Also, generate a second signal that is one every time the clock is about to roll over. (Might be easier to delay the counter by one, and then use: { o_stb, counter } <= counter + increment; together with o_counter <= counter) Use the top N bits of the counter in your counter to generate a sine wave via either a cordic or a table lookup. If using a cordic, use the o_stb value from earlier to enable a logic circuit that selects between two magnitude values, using them as input to the CORDIC If you are just using a table lookup, then multiply the output of the lookup by the same magnitude value That should get you pretty close, no? Now, if I wanted GPS synchronization, I'd start with a core I'd written for that purpose. This core keeps track of the timing since the top of a GPS second in a 2^32 bit counter. If you multiply that counter by 1000 rather than adding the increment to it as we did above, then you should have a 1kHz tone synchronized to GPS. Dan Thank you very much @D@n Link to comment Share on other sites More sharing options...
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chaitusvk
I want to generate the signal as shown below , i have pwm wave and sine wave generated(12 bit from DDS compiler) please guide how i can generate the Amplitude modulated wave from that
DDS compiler dont have option for amplitude setting
thanks you
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