how to interface fpga basys 3 board with analog discovery

[tuhin]

I am working in an DSP algorithm, I have generated the bitstream for that algorithm and dumped into FPGA basys 3 board (the output of the algorithm is of 16-bit wide and consists of 100 samples). Now, I need to view the waveform with the help of Waveforms software and analog discovery kit. So, how it can be done? Can anybody provide me some video or anyother  material that can solve the problem.

#So far information obtained#

In the material "Basys 3™ FPGA Board Reference Manual Overview" page no. 18, since, my data is of 16-bit wide I have connected pmod pins JB1 to JB4 to analog discovery pins 0 to 3 and  JB7 to JB10 to analog discovery pins 4 to 7 to transfer first 8-bit. Similarly, JC1 to JC4 and JC7 to JC10 are connected to the 8 to 11 and 12 to 15 no pins of analog discovery. Is the connection is ok? What will be other connections needed?

 

[jpeyron]

Hi @tuhin,

Welcome to the Digilent forums!

The logic analyzer in WaveForms can read up to 16 bits. I have attached a screen shot of where to do this in WaveForms. You will also want to connect gnd on the Analog Discovery to the a gnd pin on the Basys 3 such as on of the gnd pins on the pmod ports you are using. 

Make sure that your vivado xdc is constraining the 16 bit output correctly.

 

best regards,

Jon  

[D@n]

@tuhin,

Much as I hate to pour cold water on a good party, are you sure this is the right approach to debugging your design?  I've found simulation much easier to work with for this purpose.  1) All the internal registers and values are known, 2) It's a controlled environment, and 3) the equipment is easier to use and set up.

Dan

[tuhin]

Hi @jpeyron

I have connected pmod pins JB1 to JB4 to analog discovery pins 0 to 3 and  JB7 to JB10 to analog discovery pins 4 to 7 to transfer first 8-bit. Similarly, JC1 to JC4 and JC7 to JC10 are connected to the 8 to 11 and 12 to 15 no pins of analog discovery.

As you mentioned, I have also connected four gnd pins of FPGA to the four gnd pins of analog discovery. After that I opened the Waveforms software, added all the buses DIO 0 to DIO 15  of the logic analyzer but unable to see the dumped waveform of FPGA in the Waveforms software. Help me to solve the problem.

[tuhin]

Hi

Is it possible to display the dumped FPGA data with the help of oscilloscope present in Waveforms software. If so what will be the connections means which pins to which pins.

[D@n]

@tuhin,

Sounds like you are stuck in FPGA Hell.

The easy way out would be to simulate your algorithm and make sure that it works in simulation.

Dan

[hamster]

The Vivado virtual logic analyser is very easy to set up and use, and will give you the most accurate result for minimal effort 

[tuhin]

Hi everyone

Whether my question is clear? I need the specific answer for my question.

[JColvin]

Hi @tuhin,

From your picture that you attached, it looks like the physical setup is fine, though your Basys 3 is set to boot from whatever is stored on the SPI flash rather than a bitstream which could be a problem if the board is getting power cycled at the wrong time. I would recommend setting JP1 to JTAG rather that QSPI to help eliminate this potential problem.

However, there is no way for us to know that the bitstream that you have put on your Basys 3 outputs the individual bits to each individual I/O pin on the Pmod ports or that the Analog Discovery has been correctly configured to read the signals with the Logic Analyzer instrument outside of your claim.

I would echo the recommendations from Dan and hamster suggested of using the built-in analyzer that Vivado has or simulate it otherwise as this avoids using any additional hardware as well as any additional troubleshooting that comes with getting the hardware properly connected and synced. Alternatively, you could also attempt to show your 16-bit output on the on-board LEDs on the Basys 3 if you want a visual representation of what is happening (and proof that something is running).

Thanks,
JColvin

[tuhin]

Actually I am working in an DSP alorithm, in the top module of my verilog code I called my data as given in attatched file. But when I am dumping bitstream in the FPGA Basys 3 kit ( LEDs as output) the FPGA is not showing any output. Why? can anybody help me to solve it. (It is working properly in the simulation phase but not in hardware).

send.txt

[jpeyron]

Hi @tuhin,

Please you attach your xdc. 

Here is a verilog sine wave tutorial using readmemh that should be useful for the cosine portion of your project. 

Have you ran a  testbench for your IMF module? 

best regards,

Jon

 

[tuhin]

Hi @jpeyron

I followed the procedure as you mentioned in the link https://miscircuitos.com/sinus-wave-generation-with-verilog-using-vivado-for-a-fpga/?_ga=2.106154691.1163116266.1566581309-2054910748.1538715088. But still it is working only in simulation phase but not in Hardware platform. The top module of my verilog code and XDC files are attatched.

1.txt 2.txt

[tuhin]

I am getting this warning            [Synth 8-6040] Register i_reg_rep driving address of a ROM cannot be packed in BRAM/URAM because of presence of initial value.