Arty Multiple Interrupt Problem

[newkid_old]

I have an issue with one of my Arty interrupts.  I'm using the AXI GPIO interrupt along with the ethernet and timer interrupt(using the echo server example).  I've placed some debug code that sends over the UART that the interrupt is recognized but it locks  the Microblaze controller from there.

 

void InterruptHandler(void *CallbackRef)
{



	//dataReady = 1;							//Signals the main loop that the FIFO is full and ready to be read
	xil_printf("Interrupt found... \n\r");
	XGpio_InterruptClear(&fifoFull, XPAR_AXI_GPIO_0_IP2INTC_IRPT_MASK);

	XIntc_Acknowledge(XPAR_INTC_0_BASEADDR, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR);

}

Here's my interrupt handler code which works fine without any other interrupts.  Here is my interrupt setup routine:

void platform_setup_interrupts()
{
	XIntc *intcp;
	intcp = &intc;

	XIntc_Initialize(intcp, XPAR_INTC_0_DEVICE_ID);
	XIntc_Start(intcp, XIN_REAL_MODE);
	
	XIntc_Connect(intcp, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR, (XInterruptHandler)InterruptHandler, &fifoFull);
	
	XIntc_Connect(intcp, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR, (XInterruptHandler)InterruptHandler, &fifoFull);
	XIntc_Enable(intcp, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR);
	/* Start the interrupt controller */
	//XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);

	XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);

#ifdef __PPC__
	Xil_ExceptionInit();
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
			(XExceptionHandler)XIntc_DeviceInterruptHandler,
			(void*) XPAR_INTC_0_DEVICE_ID);
#elif __MICROBLAZE__
	microblaze_register_handler((XInterruptHandler)XIntc_InterruptHandler, intcp);
#endif

	platform_setup_timer();

#ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK
	/* Enable timer and EMAC interrupts in the interrupt controller */
	XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
#ifdef __MICROBLAZE__
			PLATFORM_TIMER_INTERRUPT_MASK |
#endif
			XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK);
#endif


#ifdef XPAR_INTC_0_LLTEMAC_0_VEC_ID
#ifdef __MICROBLAZE__
	XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
#endif
	XIntc_Enable(intcp, XPAR_INTC_0_LLTEMAC_0_VEC_ID);
#endif


#ifdef XPAR_INTC_0_AXIETHERNET_0_VEC_ID
	XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
	XIntc_Enable(intcp, XPAR_INTC_0_AXIETHERNET_0_VEC_ID);
#endif


#ifdef XPAR_INTC_0_EMACLITE_0_VEC_ID
#ifdef __MICROBLAZE__
	XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
#endif
	XIntc_Enable(intcp, XPAR_INTC_0_EMACLITE_0_VEC_ID);
#endif


}

I suspect an interrupt is being handled correctly but can't be for sure.  Any help is greatly appreciated.

Cheers

[jpeyron]

Hi @newkid_old,

I'm not seeing anything directly wrong with your interrupts.

Please attach a screen shot of you block design. 

Are you using the digilent board files?

Are you altering any of the settings in the Microblaze processor?

best regards,

Jon

 

[newkid_old]

Jon,

   Thanks for the reply.  I am using the Digilent board files for my project.  I am using the example Ethernet Echo Server that does work without my extra input on the interrupt controller.  This is hooked to the 3rd input on that IP.  The other two are as per the example which is the timer and the ethernet IP blocks interrupt.  I've tried changing the Interrupt type from Level to Edge but get the same results.

 

Thanks,

Curt