Nexys Video for DIP

[riste.karashabanov]

Hello everyone

I am a student in bachelors and I am working on a project combining Digital Image Processing and FPGA programming. The project consists of global image thresholding but should be done real-time by the FPGA and returning the output image back to PC/laptop. 

I have the Nexys Video board but I still haven't figured out how to "import" the images. Is it even possible to store data in the FPGA's buffer/RAM? 
If someone could help me with importing/exporting data I would be very grateful. My course in FPGA includes programming in VHDL instead of Verilog, so that's the one I am using.

Every information would be helpful.

[D@n]

@riste.karashabanov,

Will you be reading an image and then outputting it, or making your adjustments to an incoming HDMI feed?

Dan

[zygot]

2 hours ago, riste.karashabanov said:

My course in FPGA includes programming in VHDL instead of Verilog, so that's the one I am using.

Don't be afraid of incorporating Verilog modules into your VHDL code; as long as you don't intend to do extensive modifications to them. You can instantiate a Verilog module in your VHDL code, just as you would a VHDL component. You just need to convert the module declaration into a form that VHDL understands. ONly a very minimal understanding of Verilog concepts is needed to do this with rare exceptions.

[riste.karashabanov]

2 hours ago, D@n said:

@riste.karashabanov,

Will you be reading an image and then outputting it, or making your adjustments to an incoming HDMI feed?

Dan

reading from pc and outputting back to pc as jpg would be more convenient, but i would explore other options that would work better

[riste.karashabanov]

1 hour ago, zygot said:

Don't be afraid of incorporating Verilog modules into your VHDL code; as long as you don't intend to do extensive modifications to them. You can instantiate a Verilog module in your VHDL code, just as you would a VHDL component. You just need to convert the module declaration into a form that VHDL understands. ONly a very minimal understanding of Verilog concepts is needed to do this with rare exceptions.

Thank you very much, I didn't know that was possible. Although I've never working with Verilog before, so It's a bit confusing for me.