Why does Nexys 4 DDR Xilinx MIG Project use a 200 MHz inpu clock ?

[wfjmueller]

When I ported the w11 CPU design from Nexys4 to Nexys A7 I didn't use the SRAM to DDR component but wrote my own interface layer which queues writes and includes a 'last row buffer', see sramif_mig_nexys4d and sramif2migui_core.

I had a look at the Nexys 4 DDR Xilinx MIG Project and was a bit astonished to see that the SYS_CLK was 200 MHz

        <TimePeriod>3333</TimePeriod>
        <PHYRatio>2:1</PHYRatio>
        <InputClkFreq>200.02</InputClkFreq>

I really wonder why Digilent recommends this. It is possible to use 100 MHz, to use the board clock directly, and to avoid a PLL/MMCM to generate 200 MHz. In my design the MIG runs with 100 MHz and seems to work.

So question: What was the reason use 200 MHz (and thus an additional PLL/MMCM) ?

[D@n]

@wfjmueller,

The 200MHz clock is required to drive the IDELAYCTRL element.  Every design having a IDELAYE2 element within it must have at least one of the IDELAYCTRL elements within the design instantiated.

Dan

[zygot]

21 hours ago, D@n said:

The 200MHz clock is required to drive the IDELAYCTRL element

For this design this statement is true. Strictly speaking though IDELAYCTRL Refclk does not have to be 200 MHz. That is the only frequency that I've ever used.