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saif91

FPGA Altera how to convert image to .hex or .mif

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hello everyone,

i am using DE1-SoC Altera try convert image to .hex or .mif how?

i was working project display text at ram stocked formula .hex or .mif then i save it, show through VGA has been done!!!

i read this topic how he did his project

 

 

 

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@saif91,

In general, it's bad practice and frowned upon to ask a question about a product in their competitors forum.  :D

Hex file generation is pretty easy.  You can see a discussion of how to do it in lesson 8 of my tutorial, the lesson on memory.  You may struggle to build a big enough memory on-chip to hold such an image, though.  If you are writing NiOS code, you might find it easier to create a C-array containing the image into your C code.  Otherwise, you might wish to consider writing it to your flash yourself, and then copying it to whatever video memory you might have available to you: SDRAM, DDR3 SDRAM, SRAM, etc.

Dan

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8 hours ago, D@n said:

In general, it's bad practice and frowned upon to ask a question about a product in their competitors forum.

Actually, I'm not sure what Diglent's policy is about questions that aren't specific to Xilinx or Digilent products. The various FPGA vendors are certainly competitors but I have a hard time seeing non-commercial customers as 'competitors' regardless of which vendors' products they are using. 

I would agree that, even though some of the people who respond to questions posted to Digilent's Forum have recent experience with a variety of FPGA vendor's devices and tools, posting questions to a website dedicated to Xilinx based products when your question is specific to Intel is a good way to get bad information and probably unwise. Also, and this hasn't happened yet, I suspect that having a lot of questions about non-Xilinx devices and tools would be confusing to a lot of readers and make the experience for many of them of reading posts to Digilent's forum less useful.

Intel has a community forum as does Xilinx. Neither is, in my experience, as helpful as Digilent's most of the time. Intel is, well not Altera, and even Altera's community support wasn't that great. Digilent's Forum is a great place to ask about Digilent products and Xilinx tools. Even restricted to that it' must be hard for people to find answers that have already been posted because a a lot of questions keep getting repeated.

I do heartily suggest that it would be more appropriate to seek out answers to questions like saif1's at forums where people who hang out there are very knowledgeable about the tools and devices for the platform that you are working on. There also must be vendor agnostic forums out there somewhere dealing with FPGA development tools and devices.

My last word is that an awful lot of questions would be answered if the poster only took the time to read through the vendors' literature. If there's any practice that's bad form it's wasting other peoples time because you can't be bothered or don't have the time to read readily available literature. Everyone's time is as important to them as yours is to you.

 

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On 8/11/2019 at 4:05 AM, zygot said:

Actually, I'm not sure what Diglent's policy is about questions that aren't specific to Xilinx or Digilent products. The various FPGA vendors are certainly competitors but I have a hard time seeing non-commercial customers as 'competitors' regardless of which vendors' products they are using. 

I would agree that, even though some of the people who respond to questions posted to Digilent's Forum have recent experience with a variety of FPGA vendor's devices and tools, posting questions to a website dedicated to Xilinx based products when your question is specific to Intel is a good way to get bad information and probably unwise. Also, and this hasn't happened yet, I suspect that having a lot of questions about non-Xilinx devices and tools would be confusing to a lot of readers and make the experience for many of them of reading posts to Digilent's forum less useful.

Intel has a community forum as does Xilinx. Neither is, in my experience, as helpful as Digilent's most of the time. Intel is, well not Altera, and even Altera's community support wasn't that great. Digilent's Forum is a great place to ask about Digilent products and Xilinx tools. Even restricted to that it' must be hard for people to find answers that have already been posted because a a lot of questions keep getting repeated.

I do heartily suggest that it would be more appropriate to seek out answers to questions like saif1's at forums where people who hang out there are very knowledgeable about the tools and devices for the platform that you are working on. There also must be vendor agnostic forums out there somewhere dealing with FPGA development tools and devices.

My last word is that an awful lot of questions would be answered if the poster only took the time to read through the vendors' literature. If there's any practice that's bad form it's wasting other peoples time because you can't be bothered or don't have the time to read readily available literature. Everyone's time is as important to them as yours is to you.

 

clear, thank you

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LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.std_logic_arith.all;
 LIBRARY lpm;
 USE lpm.lpm_components.all;
 ----------------------------------------------------------
 ENTITY vga IS
 GENERIC (
 Ha: INTEGER := 96; --Hpulse
 Hb: INTEGER := 144; --Hpulse+HBP
 Hc: INTEGER := 784; --Hpulse+HBP+Hactive
 Hd: INTEGER := 800; --Hpulse+HBP+Hactive+HFP
 
 Va: INTEGER := 2; --Vpulse
 Vb: INTEGER := 35; --Vpulse+VBP
 Vc: INTEGER := 515; --Vpulse+VBP+Vactive            vbp
 Vd: INTEGER := 525); --Vpulse+VBP+Vactive+VFP
 PORT (
 clk: IN STD_LOGIC; --50MHz in our board
 red_switch, green_switch, blue_switch: IN STD_LOGIC;
 pixel_clk: BUFFER STD_LOGIC;
 Hsync, Vsync: BUFFER STD_LOGIC;
 R, G, B: OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
 nblanck, nsync : OUT STD_LOGIC);
 END vga;
 ----------------------------------------------------------
 ARCHITECTURE vga OF vga IS
         SIGNAL Hactive, Vactive, dena: STD_LOGIC;
         SIGNAL address: STD_LOGIC_VECTOR(8 DOWNTO 0);
         SIGNAL intensity: STD_LOGIC_VECTOR(9 DOWNTO 0);
   SIGNAL hPos: integer;
   SIGNAL vPos : integer;
    SIGNAL videoOn : STD_logic;
constant picture_size : Integer:=9000;
--------------------------------------------------------------

begin
 -------------------------------------------------------
 --Part 1: CONTROL GENERATOR
 -------------------------------------------------------
-- --Static signals for DACs:
 nblanck <= '1'; --no direct blanking
 nsync <= '0'; --no sync on green
 --Create pixel clock (50MHz->25MHz):
 PROCESS (clk)
 BEGIN
 IF (clk'EVENT AND clk='1') THEN
 pixel_clk <= NOT pixel_clk;
 END IF;
 END PROCESS;
 --Horizontal signals generation:
 PROCESS (pixel_clk)
 VARIABLE Hcount: INTEGER RANGE 0 TO Hd;
 BEGIN
 IF (pixel_clk'EVENT AND pixel_clk='1') THEN
 Hcount := Hcount + 1;
 IF (Hcount=Ha) THEN
 Hsync <= '1';
 ELSIF (Hcount=Hb) THEN
 Hactive <= '1';
 ELSIF (Hcount=Hc) THEN
 Hactive <= '0';
 ELSIF (Hcount=Hd) THEN
 Hsync <= '0';
 Hcount := 0;
 END IF;
 END IF;
  END PROCESS;
 --Vertical signals generation:
 PROCESS (Hsync)
 VARIABLE Vcount: INTEGER RANGE 0 TO Vd;
 BEGIN
 IF (Hsync'EVENT AND Hsync='0') THEN
 Vcount := Vcount + 1;
 IF (Vcount=Va) THEN
 Vsync <= '1';
 ELSIF (Vcount=Vb) THEN
 Vactive <= '1';
 ELSIF (Vcount=Vc) THEN
 Vactive <= '0';
 ELSIF (Vcount=Vd) THEN
 Vsync <= '0';
 Vcount := 0;
 END IF;
 END IF;
 END PROCESS;
-- ---Display enable generation:
 dena <= Hactive AND Vactive;
 -------------------------------------------------------
--ROM instantiation:
 myrom: lpm_rom
 GENERIC MAP (
 lpm_widthad => 9, --address width
 lpm_outdata => "UNREGISTERED",
 lpm_address_control => "REGISTERED",
 lpm_file => "2colom", --data file
 lpm_width => 10) --data width
 PORT MAP ( inclock=>NOT pixel_clk, address=>address, q=>intensity);

 --Create address (row number):
 PROCESS (Vsync, Hsync)
 VARIABLE line_counter: INTEGER RANGE 0 TO Vd;
 VARIABLE line_counter2: INTEGER RANGE 0 TO Hc;
 BEGIN
-- IF (Vsync='0') THEN
-- line_counter := 0;
-- ELSIF (Hsync'EVENT AND Hsync='1') THEN
-- IF (Vactive='1') THEN
-- line_counter := line_counter + 1;
-- END IF;
-- END IF;
IF (Vsync='0') THEN
            line_counter := 0;
        ELSIF (Hsync'EVENT AND Hsync='1') THEN
            IF (Vactive='1') THEN
                line_counter := line_counter + 1;
            END IF;
        END IF;

        IF (Hsync='0') THEN
            line_counter2 := 0;
        ELSIF (pixel_clk'EVENT AND pixel_clk='1') THEN
            IF (Hactive='1') THEN
                line_counter2 := line_counter2 + 1;
            END IF;
        END IF;
    address <=conv_std_logic_vector(line_counter , 9);

end process;
-------- --Assign color values to R/G/B
 R<=intensity WHEN red_switch='1' AND dena='1' ELSE (OTHERS=>'0');
 G<=intensity WHEN green_switch='1' AND dena='1' ELSE (OTHERS=>'0');
 B<=intensity WHEN blue_switch='1' AND dena='1' ELSE (OTHERS=>'0');
------
 END vga;

now am doing simple display image i save at rom as .mif to display to VGA and use clock 24 mhz but image not display not clear ?

 

1.png

DSC_2186fsdsdsdsdsdddddddddddddddd.jpg

67822343_2371536826468791_8746124676901634048_n.jpg

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@saif91,

  1. I like your picture.  You've picked a wonderful choice for many reasons.
  2. From your comments above, though, it sounds like you are stuck in FPGA Hell.  Your biggest problem is not that you don't know where your bug is though, your biggest problem is in your design process.  Desk-checking like this is really the wrong way to debug a design.  Why so?  Because with desk checking alone, you aren't guaranteed to ever find your bug.  This was one of the reasons why I wrote my beginner's tutorial--to introduce a beginner to a better design process from the very first lesson.
  3. That said, I found the first bug in your design.  This is what's known as a "Logic clock".  You should never create "logic clocks" in your design.  1) the tools don't know how to handle them, 2) such clocks rarely get promoted to the global clocking network where they belong, 3) leading to subtle and uncontrolled timing violations within the design that the tools may (or may not) detect, and 4) it tends to hide/obscure clock-domain crossing issues.  (Have you seen my list of "rules for beginning designers"?
 PROCESS (clk)
 BEGIN
   IF (clk'EVENT AND clk='1') THEN
     pixel_clk <= NOT pixel_clk;
   END IF;
-- ...

You really need to get this to work in a simulation first.  Debugging is just *so* much easier in simulation.  (It's even easier with formal methods ....)

Dan

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