zybo Zybo Z7 Pcam 5C Demo - Warnings

[Azzor]

I'm trying to run the Zybo Z7 Pcam 5C Demo...  

i'm really new at this, the instructions say:

**********************************************************

To generate the project:
1. Open Vivado 2017.4
2. In the tcl console, type "cd [this directory]/proj" and press enter.
3. Type "source ./create_project.tcl" and press enter to generate the block design for the project.

To run the demo from SD card:
1. Copy bin/BOOT.bin to the root of your SD card.
2. Set the boot jumper on the Zybo Z7 to SD.
3. Insert the SD card into the Zybo Z7 and power it on.

**************************************************

I'm using Vivado 2017.4 and i've copied the board_files to vivado software.

 

After the point 3. (Type "source ./create_project.tcl")

I get 7 warnings about some pins...    am im doing something wrong here?  I'm a newbie.

 

Can you help me out to make the demos work, thanks in advance!

*********************************************************************************************************

## create_root_design ""
WARNING: [BD 41-1306] The connection to interface pin /sw_gpio/gpio_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1731] Type mismatch between connected pins: /rgb2dvi_0/aRst_n(rst) and /v_axi4s_vid_out_0/locked(undef)
WARNING: [BD 41-1306] The connection to interface pin /blur_edge_detect_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl
WARNING: [BD 41-1306] The connection to interface pin /color_to_bw_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl
WARNING: [BD 41-1306] The connection to interface pin /invert_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl
Wrote  : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/system.bd> 
Wrote  : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/ui/bd_c954508f.ui> 
WARNING: [BD 41-721] Attempt to set value '50000000' on disabled parameter 'C_S_AXI_LITE_FREQ_HZ' of cell '/MIPI_D_PHY_RX_0' is ignored
WARNING: [BD 41-721] Attempt to set value '200000000' on disabled parameter 'kRefClkFreqHz' of cell '/MIPI_D_PHY_RX_0' is ignored
WARNING: [BD 41-721] Attempt to set value '100000000' on disabled parameter 'kRefClkFreqHz' of cell '/video_dynclk' is ignored
INFO: [digilentinc.com:ip:axi_dynclk:1.1-17] /video_dynclkFREQ_HZ of 100000000 propagated into CONFIG.kRefClkFreqHz
INFO: [digilentinc.com:ip:MIPI_CSI_2_RX:1.0-17] /MIPI_CSI_2_RX_0Verified that video_aclk frequency can handle RxByteClkHS frequency. AXI-Stream bandwidth 600000000 Pix/s >= PPI bandwidth 134400000.0 Pix/s
INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.0-17] /MIPI_D_PHY_RX_0FREQ_HZ of 50000000 propagated into CONFIG.C_S_AXI_LITE_FREQ_HZ
INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.0-17] /MIPI_D_PHY_RX_0FREQ_HZ of 200000000 propagated into CONFIG.kRefClkFreqHz
INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.0-17] /MIPI_D_PHY_RX_0FREQ_HZ of 84000000 propagated onto RxByteClkHS
Wrote  : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/system.bd> 
VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/synth/system.vhd
VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/sim/system.vhd
VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/hdl/system_wrapper.vhd
make_wrapper: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1317.461 ; gain = 79.957
# set sdk_dir $origin_dir/sdk
# set hw_list [glob -nocomplain $sdk_dir/*hw_platform*]
# if {[llength $hw_list] != 0} {
#   foreach hw_plat $hw_list {
#     file delete -force $hw_plat
#   }
# }
# set sdk_list [glob -nocomplain $sdk_dir/*]
# set sdk_list [lsearch -inline -all -not -exact $sdk_list "../sdk/.keep"]
# if {[llength $sdk_list] != 0} {
#     exec xsct -eval "setws -switch ../sdk; importproject ../sdk"
# }
update_compile_order -fileset sources_1

[jpeyron]

Hi @Azzor,

Welcome to the Digilent forums.

I downloaded the zip file for Vivado 2017.4 from the release page here. I opened Vivado 2017.4 cd'd to the correct folder and opened the project. I then generated a bitstream without issue.

I have attached a screen shot of this.

Are you using a different version of Vivado?

Best regards,

Jon

[artvvb]

To add a little bit to what Jon said, these warnings appear to be ignorable. They all relate to design choices made when connecting custom IP in the block design.

Typically, even when designing with Xilinx IP, many warnings are seen in the project. These messages are there to help get information on why something may be causing bigger problems later (errors, critical warnings, something not working in actual hardware). Note that even some critical warnings may be ignored.

-Arthur