Overall direction and method of design with zynq.

[sungsik]

Hi. I'm beginner of zynq. 

When I was designing with hdl on spartan6, I drew a timing diagram and designed a state machine to make the desired signal

from the desired state.

So, I've already designed a state machine. However, I am not sure because I am going to use this state machine in combination

with the aurora ip and gpio ip of xilinx. I want to design to interact with gpio1 in some states and gpio2 in others state. 

(i mean that read value from gpio to PL side in specific state.)

For do that, do i design a state machine in custom axi ip? Can i control it only with hdl? Or do I have to control it with C code in SDK?

 

I'm sorry that the question is not clear because I don't know well.

Thanks.

[D@n]

@sungsik,

So let me shoot in the dark and ramble and see if it helps clarify your question.  There are many ways you can design things on a Zynq.

1. You can create state machines like you did before on the Spartan 6, making logic just like before that will work without a CPU.  Indeed, you can still control I/Os like before if you want.  The AXI GPIO core may be nice, but it is certainly not required.
2. You can create AXI slave cores.  Anything you create with a slave interface can be connected to the ARM in the Zynq and can interact with the ARM.  This is typically very useful for controlling peripherals from the PS.  You would write software commands to interact with your device, and off you go.  This might be the easy way to interact with the AXI GPIO, but it is by no means the only way.  There's also a discussion to be had about where the O/S / Application division will be within your software and how to write a proper device tree entry for IP cores that will be controlled from Linux.
3. You can also create AXI master cores in PL.  Your AXI masters can then be used to drive AXI slaves.  So, for example, if you wanted to control the AXI GPIO as a state machine on board, all you would need to do is to connect an AXI master to it to do so.   This would apply to any DDRx SDRAM as well.  Yes, it is possible to connect an AXI master to multiple slaves, this requires an interconnect however.

Which method you choose is up to you, the designer, and the specific and particular needs of your project.  For example, logic is limited but fast, whereas software  tends to be abundant but not nearly as fast.  Further, most CPU software will produce (fairly) unpredictable timing, where as timing can be tightly controlled from the PL.

Hopefully these ramblings will at least suggest where the conversation might go next.

Dan

 

[sungsik]

Thanks for reply, @D@n.

I want to control AXI gpio as a state machine, so option3 (creating AXI master cores in PL) is proper to me.

At same time, i want to control them by processor.

This is my overall structure.

 

Once again, I am sorry for my vague question.

[xc6lx45]

stating something that may be very obvious (or not):

You don't need a GPIO IP to drive IO pins. If you have your own RTL block already, it's a three line job in Verilog / VHDL.

[sungsik]

Thanks.@xc6lx45 .  Yes, Starting new thing  always hard but fun.

I want to change IO value through PC. So i think it can be done by using xilinx library in SDK . Is there any better method?

[xc6lx45]

On 8/2/2019 at 2:28 AM, sungsik said:

So i think it can be done by using xilinx library in SDK . Is there any better method?

Question is, what's "better". If I'd use standard AXI blocks and SDK, the motivation would be that other people can work easily with the design, using the higher-level description. This would be my strong preference. Also, that you can have working code within about 60 seconds.

If your project is large enough to warrant a more "efficient" implementation (keeping in mind that Xilinx is motivated to sell silicon by the square meter, not to use it at maximum efficiency), a custom RTL blocks and direct access via volatile unsigned int pointers. But for "controlling it via a PC" this is simply not relevant.