ARTY A7 instantiate PLL in top module

[skylape]

Hello everyone,

I am facing a problem create an instant of the PLL I setup from the Clocking Wizard. My goal is to provide my PWM module a much faster clock than the 100MHz one. I am extremely new on verilog programming (I know nothing of this stuff yet lol). My current code throw my 16 errors code that I know absolutely nothing about. Any helps on this would be greatly appreciate. 

Thank you reading 

P/s: The below text is my top module.

module top(
    input CLK,
    input fastClk,
    output pwm_out1,
    output pwm_out2,
    output pwm_out3,
    wire rst,
    wire lck
   
);
clk_wiz_0(.clk_out1(fastClk),.reset(rst),.locked(lck),.clk_inl(CLK));
pwm pwm_output1 (
    .clk(fastClk),
    .i_duty(10),
    .pwm_out(pwm_out1)
);
    pwm pwm_output2 (
.clk(fastClk),
.i_duty(45),
.pwm_out(pwm_out2)
);
    pwm pwm_output3 (
.clk(fastClk),
.i_duty(80),
.pwm_out(pwm_out3)
);
endmodule
 

[jpeyron]

Hi @skylape,

Welcome to the Digilent Forums!

Here is how you would instantiate the clocking wizard with default names. In the below example there are 2 output clocks.

clk_wiz_0 clk_1

(

// Clock in ports

.clk_in1(CLK100MHZ),

// Clock out ports

.clk_out1(clk_out_100MHZ),

.clk_out2(clk_out2_200MHZ),

// Status and control signals

.locked()

);

end component;

 

Here is a verilog project for the Nexys Video that used the clocking wizard. Here is a VHDL project that used the clocking wizard for the Arty-A7-35T. You can add the IP through ip catalog.

best regards,

Jon

[skylape]

3 hours ago, jpeyron said:

end component;

 

Do I need to include this at the end of every instance I create? Because in my top.v I have total of 4 four different instance ( pwm_output1, pwm_output2, pwm_out3 and the clk_wiz one)

[skylape]

3 hours ago, jpeyron said:

Hi @skylape,

Welcome to the Digilent Forums!

Here is how you would instantiate the clocking wizard with default names. In the below example there are 2 output clocks.

clk_wiz_0 clk_1

(

// Clock in ports

.clk_in1(CLK100MHZ),

// Clock out ports

.clk_out1(clk_out_100MHZ),

.clk_out2(clk_out2_200MHZ),

// Status and control signals

.locked()

);

end component;

 

Here is a verilog project for the Nexys Video that used the clocking wizard. Here is a VHDL project that used the clocking wizard for the Arty-A7-35T. You can add the IP through ip catalog.

best regards,

Jon

Since I only a highspeed clock and nothing else for the moment, my clk wizard only have clk_in1 and clk_out1, so I removed the .locked() from your example. and I tried to run the code again and it still failed to compile. Can you help me take a look into it?

`timescale 1ns / 1ps

module top(
    input CLK,
    input fastClk,
    output pwm_out1,
    output pwm_out2,
    output pwm_out3  
);
clk_wiz_0 clk1 (.clk_out1(fastClk),.clk_in1(CLK));

pwm pwm_output1 (
    .clk(fastClk),
    .i_duty(10),
    .pwm_out(pwm_out1)
);
    pwm pwm_output2 (
.clk(fastClk),
.i_duty(45),
.pwm_out(pwm_out2)
);
    pwm pwm_output3 (
.clk(fastClk),
.i_duty(80),
.pwm_out(pwm_out3)
);
endmodule

 

The below attached pictures is my error codes

[jpeyron]

Hi @skylape,

 

I believe the Verilog module should use the fastclk as a wire connecting the output from the clocking wizard to the pwm module. 

`timescale 1ns / 1ps

module top(
    input CLK,
    output pwm_out1,
    output pwm_out2,
    output pwm_out3  
);

wire  fastClk;

clk_wiz_0 clk_1

(

// Clock in ports

.clk_in1(CLK),

// Clock out ports

.clk_out1(fastClk),

// Status and control signals

.locked()

);

 

pwm pwm_output1 (
    .clk(fastClk),
    .i_duty(10),
    .pwm_out(pwm_out1)
);

    pwm pwm_output2 (
.clk(fastClk),
.i_duty(45),
.pwm_out(pwm_out2)
);
    pwm pwm_output3 (
.clk(fastClk),
.i_duty(80),
.pwm_out(pwm_out3)
);
endmodule
 

You will also need an xdc file to constrain the input and output signals to pins on the FPGA. Here is the master xdc for the arty-a7.

best regards,

Jon

 

[skylape]

Hi @jpeyron,

Thank you for the solution, I was able to generate bitstream but there is a Timing problem that Im not familar with. I suspect that the Timing problem is why when I hook up the board to the oscilloscope, I wasnt able to trigger the pulse and I noticed that the device was skipping pulse. Do you have any suggestion regarding this?

P/s: The attachments are the timming error summary and the schematic for the design. 

[jpeyron]

Hi @skylape,

I would suggest simulating your project.  

best regards,

Jon

[skylape]

Good morning @jpeyron,

During simulation, I couldnt identify the issue, everything runs fine. Atm, I could not  see the reason why my code have timing errors in it. The code doesnt seems to be complicated to create some routing issue imo.  I think the issue rely in the PLL I create. Any recommendation to fix this ?

 

[jpeyron]

Hi @skylape,

Sorry for the confusion. I was referring to creating a testbench and simulating the project so to better see the signals. Here is a YouTube video about making a testbench. 

best regards,

Jon

[skylape]

1 hour ago, jpeyron said:

Hi @skylape,

Sorry for the confusion. I was referring to creating a testbench and simulating the project so to better see the signals. Here is a YouTube video about making a testbench. 

best regards,

Jon

I did make the testbench file and run the simulation. The signal Im getting on it is perfectly good. I think that the clk routing causes the timming error which subsequently makes the board skipping beat. Maybe the clock got skewed big time?

 

[jpeyron]

Hi @skylape,

Please attach your Verilog top and pwm modules and i will see what i can do to get it working on an Arty-A7.

best regards,

Jon

[skylape]

@jpeyron Here is the compress srcs file. Again thank you so much for this. 

 

PWM_5MHz Trial 2.srcs.zip

[jpeyron]

Hi @skylape,

I made a vivado 2019.1 Arty-A7-35T project using the pwm.v module and adjusting the top.v. I have attached a screen shot of the output on the first three pins on pmod Port JB. I have also attached the files I used and the generated bit file.

best regards,

Jon 

 

pwm.v top.v arty.xdc top.bit