Sync Digital Discovery Pattern Generator With External Clock

[akeener]

Hello @attila

Is there any way that I can synchronize the pattern generator on the digital discovery with an external clock? I need to ensure that pulses on the pattern generator are aligned with the clock edges. The clock base between the digital discovery pattern generator and the logic circuit I am interfacing with needs to be the same for the signals to be clocked correctly. Thanks!

[attila]

Hi @akeener

On Digital Discovery the pattern generator can trigger on external trigger signal through logic analyzer trigger detector. It will have a delay of about 200ns.

See the following related post:

 

[akeener]

@attila I am currently doing that to initiate the pattern generator, but the issue is maintaining a synchronous state with the external clock signal during the pattern generation. For my case, I am clocking a digital logic circuit with a 20MHz oscillator, and I need to send digital signals that are synchronous with the clock from the Digital Discovery to the circuit. This is a necessity for testing a rising edge clocked digital circuit and ensuring that the data is clocked in correctly. 

 

[attila]

Hi @akeener

The independent oscillators will have jitter, phase shift in time.
You could use the wait-run-repeat -repeat trigger options in the Pattern Generator to periodically re-synchronize with the circuit.
You could also use the Digital Discovery Pattern Generator to generate the needed 20MHz clock. This way your circuit will be in phase with the other signals.

[akeener]

@attila

Generating the clock signal from the digital discovery would not solve the problem in my case as I have four digital discovery modules that need to be synchronized on the same time base. The repeat trigger option does not work well for all my different test cases as I can be generating up to 64 independent signals at a time. Is there any other way to use an external clock for the pattern generator, essentially the same way you can use the sync option for the logic analyzer?

[attila]

Hi @akeener

The ROM Logic might be useful: