Arty Z7 DDR/UART access without the PS

[okonomiyonda]

I'm just getting started with FPGAs, Arty, and Zynq, so I apologise if this is a beginner question or what I'm saying doesn't make total sense.

I'm trying to figure out how to read/write DDR and use the UART from the FPGA side with no involvement from the CPU/PS. I've seen Vivado tutorials where you connect the FPGA over AXI and have the CPU sit in a while loop and printf to the UART. I've seen Vivado tutorials where the CPU sits in a while loop, waits for AXI data or interrupts from the FPGA, reads data from memory, flushes the cache, and sends the data to the FPGA. What I can't seem to find is any examples of the FPGA directly talking to DDR and UART.

What I know so far:

Starting with the image here, it looks like the PL side should be able to talk to DDR and UART over the AMBA interconnect through AXI ports. And indeed, the docs say "cores implemented in the PL can trigger interrupts to the processors (connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory" which at least makes me think DDR should be accessible to the FPGA via AXI DMA without PS involvement. I just can't find an example of what I need to do in Vivado to get this hooked up. Separate question: It looks like the PS has a direct connection to DDR that doesn't go over AMBA, so I am wondering what has priority in DDR access, and what the approximate order of magnitude speed difference between CPU uncached direct access and AXI DMA access from the FPGA would be.

Maybe the picture is different for the UART, where I see "the peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space". Again, it looks like both the PL and peripherals are connected to the AMBA interconnect, albeit both as slaves. It also seems that peripheral control registers are only accessible in the processes memory space, but if I can rely on the default reset values, maybe that's not a problem?

So the TL;DR version is Is it possible to read and write DDR from the FPGA without PS involvement? Can I use the UART from the FPGA without PS involvement? Are there any good samples out there I could reference?

Edited July 15, 2019 by okonomiyonda
adding a question

[zygot]

1 hour ago, okonomiyonda said:

What I can't seem to find is any examples of the FPGA directly talking to DDR and UART.

Well you get points for doing some research. I suggest that you start with reading the Xilinx literature for the ZYNQ device on your board to see how the PS and PL connect. Then look at the schematic for your board to see what the various interfaces connect to. If you look on page 8 of the Arty 7 schematic you'll see that the DDR and UART signals are connected to PSxx pins or PS_MIOxx pins; that is to the PS. A few ZYNQ boards have DDR and or Ethernet connected to PL pins but most like the Arty7 have all of the user interfaces connected to the PS. SO... tying off the PS and just using the PL, something that is possible by the way, is going to be difficult for what you want to do. Neither the UART or DDR for the Arty 7 are connected to the PL. It is possible to create a program running as a bare-metal application to service an AXI connection between some design in your PL and the PS to allow you to connect a TTL USB cable to PL pins to a UART in your design. There are a number of options for building proper AXI interfaces to your PL HDL code and I like to use BRAM. Since your interface is a UART a DMA interface seems a bit extreme to me on face value... but I haven't tried to do this. My personal preference for ZYNQ designs is to have the bare minimal board design functions needed to connect the PS to the PL. I then use the HDL entity or module created by Vivado representing the board design as a component in my toplevel HDL design file where all of my real design goes. 

I'm not quite understanding what exactly it is that you envision as the layers of hardware involved but you can't read/write directly to DDR from either the PS or the PL. Both have external memory controllers that are quite complicated, though on the PS side most of it might be something that you can ignore. Perhaps starting off with a simpler design concept; like creating a bare-metal PS application to read PL registers for address, write data etc and write other PL registers like read data. Given typical UART speeds a polled service should be usable. That project will be more than enough to keep you busy for a while.

I'm curious as to why you would want to do a ZYNQ project without the ZYNQ.

Edited July 15, 2019 by zygot

[Sheraz]

On 7/15/2019 at 11:33 PM, okonomiyonda said:

I'm just getting started with FPGAs, Arty, and Zynq, so I apologise if this is a beginner question or what I'm saying doesn't make total sense.

I'm trying to figure out how to read/write DDR and use the UART from the FPGA side with no involvement from the CPU/PS. I've seen Vivado tutorials where you connect the FPGA over AXI and have the CPU sit in a while loop and printf to the UART. I've seen Vivado tutorials where the CPU sits in a while loop, waits for AXI data or interrupts from the FPGA, reads data from memory, flushes the cache, and sends the data to the FPGA. What I can't seem to find is any examples of the FPGA directly talking to DDR and UART.

What I know so far:

Starting with the image here, it looks like the PL side should be able to talk to DDR and UART over the AMBA interconnect through AXI ports. And indeed, the docs say "cores implemented in the PL can trigger interrupts to the processors (connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory" which at least makes me think DDR should be accessible to the FPGA via AXI DMA without PS involvement. I just can't find an example of what I need to do in Vivado to get this hooked up. Separate question: It looks like the PS has a direct connection to DDR that doesn't go over AMBA, so I am wondering what has priority in DDR access, and what the approximate order of magnitude speed difference between CPU uncached direct access and AXI DMA access from the FPGA would be.

Maybe the picture is different for the UART, where I see "the peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space". Again, it looks like both the PL and peripherals are connected to the AMBA interconnect, albeit both as slaves. It also seems that peripheral control registers are only accessible in the processes memory space, but if I can rely on the default reset values, maybe that's not a problem?

So the TL;DR version is Is it possible to read and write DDR from the FPGA without PS involvement? Can I use the UART from the FPGA without PS involvement? Are there any good samples out there I could reference?

@okonomiyonda I hope you are doing Fine.

I want to accomplish the same as u described.
I have a USB to TTL converter and I wish to hookup external interfaces from the block design to the EMIO pins on the board.
Can u point me towards some helpful samples or documents.
 

Reagrds,