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Spartan®-3E 1600 FPGA Starter Kit board has an LCD on it


Hi All,

Phil here again.  I have Spartan®-3E 1600 FPGA Starter Kit board and it  LCD on it.  The first problem  I am having missing the FPGA pin number for LED 0.

Tried the Xilinx the Spartan 3E manual.   All the LEDs in this datasheet are wrong.  The PCB board is correct.  However, I can't read the LED(0) number.

Any ideas,  if one does not know about these pins. Maybe there are tools that I could use to narrow down the possible location of this LED 0 pad on this PCB.  

Looking for the FPGA pad number?    Thanks.

The second thing I would like to do. Writing to the LCD in 4-bit mode and turning off the memory chip in the process.  CE of the memory is vital as well as the display.

Not sure how when the memory is addressed for the FPGA chip.  Either way, I would love to write to this display while the memory is not being used.  and go back to a high impedance

state when not writing to display.   I guess I am looking for the timing diagram for the LCD display and memory.


The third item I am having is how does this Cool Runner II  CPLD on this board work.   It appears it's hanging out on the upper ram and rom memories.   Does anyone have this JED Code for this CPLD?   Can I extract the code from the JTAG link and display it in VHDL using ISE tools?   Is this chip necessary to have in production runs?   Are the newer board build with this in place?

Thanks for your help.  Soon I will be in the Spartan 7 stuff.   I have legacy equipment that I am still supporting.  Spartan 3 stuff.  One day we can push for the newer stuff.

I use trainers to keep current somewhat? 



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Hi @pgmaser,

You can find the details for the what FPGA pin is associated for the Spartan 3E-1600 in it's user guide that Xilinx created (available on the right hand side of it's Resource Center under Documentation, conveniently linked here for you. LED0, as per page 18 under Discrete LEDs, is linked to D4. This is verified on page 4 of the schematic as well. I presume you were looking at the Spartan 3E starter kit user guide which is using a 500 variant of the Spartan 3 rather than a 1600 variant of the Spartan 3, hence the difference in FPGA pins.

An example UCF file for the entire Spartan 3E 1600 is available at the end of the previously mentioned user guide starting on page 163.

I am not certain what you mean by "writing to the LCD in 4-bit mode and then turning off the memory chip in the process". Are you referring to the memory chip present on the LCD screen? Based on the Memory Map section on page 44 of the user guide, I don't think you would be able to write to the display while having the memory turned off, though you can just keep the LCD screen turned off with the display off command, fill in whatever you like to the display memory, and then turn the display back on. As for a timing diagram, you would have to find the datasheet of the Sitronix ST7066U graphics controller or one of the functional equivalents that are also listed on page 44 of the user guide.

The CPLD (as per page 127 of the user guide) coordinates behavior between the different FPGA configuration memories such as the two PROMs, so if you are using the flash memory, I imagine it is needed for production runs. I don't believe we have the JED code available for it, nor do I think it is readily possible to extra the configuration and display the HDL on ISE, though I am not very familiar with that end of things.

Thank you,

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