Question

Dear Team,

We have established Ethernet communication on Arty-7 35 T  for FPGA to PC (Transmission) and PC to FPGA (Reception). We have done RTL design without using micro-blaze and On system side we are using Visual studio for sending commands to FPGA using socket programming. We are facing following problems which are given below :

  • FPGA to PC communication works perfectly for any IP address, but When we send command from socket  for PC to FPGA communication, Ethernet on FPGA only listen to xxx.xxx.1.255 - broad cast IP. FPGA does not listen to any other value than 255. What could be reason behind this?
  • Another problem we observed related to wire shark. While having Ethernet communication, If we close wire-shark, FPGA stops sending data. We are not able figure the main cause.

 

 

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@core2explore,

  1. The first issue you are having is the result of the PHY you are using.   In my own Arty controller, I (optionally) filter out all packets but those with my own IP address or the broadcast address (255.255.255.255).  How you build your own controller is up to you.  I know mine is published on line and there's also a liteeth core published on line.  In both of those cases, you should have no problems looking through the controller code to see what's going on.
  2. Wireshark places your PC's network into what's known as "promiscuous mode".  In this mode, it reports all packets given to it without the filter of whether or not the packets are for the local PC.  Chances are  you have either an ethernet address mismatch or an IP address mismatch causing this problem.

Many new individuals working with networks don't realize that you also need to communicate and respond to ARP packet requests.  If you failure to respond to ARP requests, the PC will never "find" the FPGA-based ethernet.  Likewise, if you fail to issue and process the responses of ARP packet requests, your  solution will only ever work  on a single network with known ethernet and IP addresses.

Dan

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10 hours ago, D@n said:

Many new individuals working with networks don't realize that you also need to communicate and respond to ARP packet requests.  If you failure to respond to ARP requests, the PC will never "find" the FPGA-based ethernet.  Likewise, if you fail to issue and process the responses of ARP packet requests, your  solution will only ever work  on a single network with known ethernet and IP addresses.

I'd say that this could be better stated. There are three flavors of ARP packets. The gratutious ARP should be sent out from the FPGA at some low repetition rate. The purpose of this packet is to advertise the existance of your device to other devices privy to it's connection The switch or device at the other end updates the IP address tables periodically. Once every 2-10 seconds should suffice. Request ARP packets are sent out by a device to see if it is connected. [edit] The response ARP let's other devices looking for a device at your Ethernet address by sending a request ARP know that you are still alive and ready to talk; so you need to reply to them.  You need to make sure that all of the address fields in your outgoing packets have the correct address, which might be the broadcast address. Periodic GARP messages can be useful in debugging your connection.

As to your addressing issues I don't know how your HDL does packet parsing and creation. Perhaps there is a hard-coded address somewhere. If you mess up the CRC generation in any of the packets that your FPGA sends, or the payload length,  it might not be recognised or accepted on the other end. I suspect that your code has an error in on of the address fields, CRC or length specifications.

I've found wireshark to be minimally useful though it does help developing a software Ethernet client application. You may have to read between the lines of what wireshark tells you.

Nice work... keep on trucking!

Edited by zygot

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One more thought that may or may not be a problem for you. In a closed system with a limited number of packet types, and nodes, and rules for when a node can transmit packets or not  you don't have to worry about fragmentation or collisions. When one of your nodes is a PC this might not be true. Obviously, these two scenarios greatly complicate the FPGA design if they need to be handled properly.

Edited by zygot

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