Signals From PMOD Basys 3 Ports

[AJ_Horto]

I recently created a System Verilog code to measure latency between two incoming pulses. I tested it with buttons on the board first and it worked. Now that I'm using the PMOD ports, however, it just keeps on reading that the pulses are always high, though nothing is connected to them. The only thing that I've changed is the XDC file. Why can't I use the PMOD Ports?

[AJ_Horto]

hi, @D@n and @jpeyron,

I seem to still be having the same problem. The pmod ports, whenever I use them, for any input, are always high, regardless of what I do. Like I said, I tied one of the ports as an input directly into another as an output and directly into an LED. Although the input port had no voltage(when measured by a MultiMeter), the output port had 3.3V and the LED was on.

I have no idea why the PMOD ports aren't allowing inputs(or why the signal is being driven High). If there is any more help that I could receive, it would be much appreciated.

 

Thank You for all of your help,

AJ

[AJ_Horto]

hi, @Bianca @jpeyron

Using the physcial Pin and the pulldown semed worked. Thank You guys so much for your endearing patience with me!! I cant thank you enough!!

 

AJ

[Bianca]

@AJ_Horto, @jpeyron,

Another way would be to physically connect the pmod pin to GND with a wire. In that way you are not relying just on the FPGA pulldown. If the led would be still on after the pin is physically wired to GND, then the board is defective. 

Cheers,

Bianca

[jpeyron]

Hi @AJ_Horto,

The mode jumper JP1 should be set to JTAG and not USB. The USB mode is for configuring the FPGA from a USB thumb drive as described in the reference manual  here in section 2.3 USB Host Programming on page 5. 

I was able to get the led's to turn on if i were to touch the exposed pins on the pmod ports. To ensure that there is not a false logic high I added the pull down option in the xdc for the unused pins as well as JA[0] and JA[1]. 

Please configure the Basys 3 with the below attached bits file as well as make sure to have the mode jumper set to JTAG.  led_ja.bit ties the leds to JA[0] and JA[1].  led_jb.bit ties the leds to JB[0] and JB[1].

Did the leds stay on when using the pmod port JA and led_la.bit? 

Did the leds stay on when using the pmod port JB and led_jb.bit? 

best regards,

Jon

 

 

Basys3_sw_Demo.xdc led_ja.bit

led_jb.bit

[AJ_Horto]

I am powering the Basys 3 via USB, and I have both jumpers set to USB for the shorting blocks. Attached are pictures of the setup with your bit file loaded onto it.

The Seven Segment is dimly lit, I assume this to be the same problem from the thread that you recommended me to. I am not very concerned with that one. But as you can see, no inputs are going into the PMOD ports.

[jpeyron]

Hi @AJ_Horto,

Led[1] should only be on when JA[0] is logic high and Led[2] should only be on when JA[1] is logic high.

Please attach a picture of your set up.  Is the mode jumper JP1 set to JTAG?

How are you powering the Basys 3?

best regards,

Jon

[AJ_Horto]

I just downloaded the bit stream and the two LEDS are on even without any input on any of the ports. Is that what it was supposed to do?

[jpeyron]

Hi @AJ_Horto,

I haven't used system verilog much but i have used verilog and vhdl much more. I have attached a confirmed basic verilog module that ties 1 led to JA[0] and another led to JA[1](I altered an existing module so the naming convention is incorrect).

Please configure the Basys 3 with the attached bitstream. Does an led turn on when the JA[0] or JA[1] is given 3.3v?

best regards,

Jon

sw_led.v Basys3_sw_Demo.xdc sw_led.bit

[AJ_Horto]

Hey @D@n,

Sorry but I have already done so, the XDC and top level are posted above in this thread already. there are some differences, but read the text associated with each reply, and you will understand.

[D@n]

Double check that your XDC file matches the top level file of your design, and that the input names match those in the XDC file.

Dan

[D@n]

You should be able to accept inputs from the PMod ports without problems.  Be aware, the PMod's are 3.3V.  If you want something else, you'll need a level shifter.  But ... that's about it.

If you do have a problem, please post and we'll help you through whatever it might be,

Dan

[AJ_Horto]

Hello @jpeyron,

Yes, I plan on using a generator to initially test the program. When pulling down signals, does it tie it to a low output?

I also tested something yesterday that has me very confused. I wanted to see V_out on the PMOD ports if they were actually being driven high.

I tied one output port on the PMOD directly to an input from the PMOD. I wanted to see if the the input being seen as high would drive the other port to have 3.3V. And it did exactly that. It seems like I am not supposed to have input from teh PMOD ports?

 

Am I not supposed to input logic into the PMOD Ports?

 

Thank You,

AJ

[jpeyron]

Hi @AJ_Horto,

The buttons are tied to gnd unless it is pressed. The buttons are not left floating as shown on page 15 of the reference manual for the Basys 3.  Here is a forum thread that discusses using "BITSTREAM.CONFIG.UNUSEDPIN Pulldown". It might be good to pulldown JA [0] and JA [1] as well.

Are you planning on using a waveform generator when testing JA [0] and JA [1]?

best regards,

Jon

[AJ_Horto]

Unfortunately, Still no. I'm rerunning an implementation for using the buttons to test. I could connect the pins to two of the *buttons* on the FPGA and run the pulses through those, but I'd prefer to use the headers.

 

Thank You so much for your quick replies,

AJ

[jpeyron]

Hi @AJ_Horto,

To clarify, is you new project working now?

best regards,

Jon

[AJ_Horto]

Okay, the two images attached are the top level for what I was using. The first image is what I had, and the second is what I changed it too after your last comment. It is running the implementation now.

[jpeyron]

Hi @AJ_Horto,

Did you change the pin names in your system verilog to match the JA[0] and JA[1]?

Might be easier to just change the xdc JA [0] and JA [1] pin names to btnl and btnr if you haven altered the system verilog file. 

please attach the top/wrapper file for your system verilog for the previous and current project.

best regards,

Jon

 

[AJ_Horto]

Attached is the xdc that I used. When I switched to the JA PMOD ports, all I did was comment out the btnl and btnr pins, and uncomment the JA[0] and JA[1] pins. It's not the same as the master xdc, but the other parts of the xdc have linked up just fine.

Thank You so much for your help!

AJ

[jpeyron]

Hi @AJ_Horto,

Are you using the master xdc for the Basys 3 from here?

Please attach your previous xdc with the buttons and your current xdc.

best regards,

Jon