joaquinbvw

Cora Z7-10 High-Speed Pmods

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Hello! I just signed in to the forum, happy to be part of it.

I have a question regarding the High speed Pmod connectors on the Cora Z7-10, I want to know what is the speed limit of each differential pair. I want to use the Cora Z7 for a data acquisition system, some ADC boards will be connected to these Pmod connectors and will send data trough it.

My ideal case will be to transfer data from 8 ADC boards, each of them have 14 bits and are sampling at 60MHz, so each differential pair will have a speed of 840 Mb/s. Is this possible with the Cora Z7-10 High-Speed Pmod connectors? If not, what is the maximum speed of those connectors?

Thank you for your time.

Cheers,

 

Joaquín

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Hi @joaquinbvw,

Sounds like an interesting project. Unfortunately, we do not have a maximum data rate metric for the high speed Pmods. Here and here are forum threads that discusses the high speed pmod ports.

best regards,

Jon

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Thank you Jon! I will check those threads and on the next days I will try some tests with a couple of boards I have.

Cheers,

Joaquín

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Posted (edited)
On 7/8/2019 at 6:07 PM, joaquinbvw said:

My ideal case will be to transfer data from 8 ADC boards, each of them have 14 bits and are sampling at 60MHz, so each differential pair will have a speed of 840 Mb/s. Is this possible with the Cora Z7-10 High-Speed Pmod connectors?

A word of caution. You will likely be using ISERDES. Just having pins available is not sufficient. You need to understand the clocking aspect of your interface. There are limitations with respect to where interface clocks and data pins can be assigned. Moreover your requirement for 14X data rate to reference clock rate is more complicated than just a simple LVDS interface. I've posted on this a few time already; particularly on the incompatibility of Ti ADC EVMs connected to the FMC connector.

I would be very surprised and very impressed if you can do what you want to do with any of the Digilent board high speed PMOD connectors. Very few of them even connect to clock capable pins. There's a lot of homework to do before buying hardware for a project like yours.

I suggest that you look into Opal Kelly's SYZYGY compatible boards. They have one with a ZYBQ and one without but the IO ports are well designed for such an interface.

One day Digilent might offer boards with sensible IOSERDES compatible IO connector designs but NOT today.

[edit] In all fairness the Nexys Video and Genesys2 FMC connectors are well designed and if you are prepared to make your own mezzanine EVM adapter or ADC board then these are good options [if you know what you are doing]

Edited by zygot

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Hi zygot,

thank you for your response, I appreciate it very much! You're right, just using LVDS is not enough, I was just trying to see if there were maximum speed tests on that interface. At the end I'm planning to use JESD204B for this application, since that interface was design for this type of requirements. The Cora z7 board is just for testing, in the future we will be building our own board for the acquisition system we want to implement.

I'm new to this JESD204B protocol/interface but I know that it has a lot of advantages and a lot of Analog Devices high speed ADCs use it, that's why I want to use that. There are some problems using the Cora z7 that I found, it seems that the traces that goes to the PMOD connectors are designed for LVDS, so it is a different impedance matching. I guess if I adapt it well on the other side the JESD204B could be used (it seems that they use CML interfaces for the data lines in this JESD204B protocol). And also you're right on the clock issue, I didn't see if any of the PMOD pins goes to any clock pin, I will have to check this also.

We will be doing some tests in the next days, I will post our results here so you can see it and maybe help me with some questions.

Thank you again.

Cheers,

Joaquín

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Posted (edited)
3 hours ago, joaquinbvw said:

t the end I'm planning to use JESD204B

All of the JESD204B implementations that I've seen use transceivers, perhaps this explains your observation of the CML logic. Transceivers have a different clocking issue (MGT quad specific pins). I suggest that you immerse yourself into the clocking, Series7 IO, and transceivers User's Manuals provided by Xilinx before getting too far ahead of yourselves. As I mentioned previously, there is a lot of research to do before selecting hardware.

I do believe that JESD204B compatible ADCs and DACs are the way to go though you either have to pay for IP or spend some time developing your own IP.

I hate when I feel obliged to say this.... but.... you really might want to consider that other FPGA universe (Intel) for data conversion projects. Intel isn't very friendly to those with a minimalist budget but there are a lot more options with HSMC.. though lately even that standard has gotten fractured. Don't expect to be able to use an FMC ADC EVM designed for an Intel based FPGA board with a Xilinx development board.  If you do decide to try out a third party JESD204B ADC card make sure that you can actually use it for development purposes. The only way to test this is to be able to re-create the vendors demo projects ( from scratch without components missing for encrypted netlists as sources...) with your own tools, for you own target. Oh, and make sure that the analog front end is compatible with your needs, especially with ADCs optimized for comms applications. Read the notes, read the lines, read between the lines.

I have a DEV-ADC34J22 EVM from Ti that was designed by Dallas Logic and except for using the provided bitstream for a specific target the board is worthless. There are a lot of sand traps lurking about the hole that you want to play on.

Edited by zygot

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