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charlieho

Implement simulation for FIFO with MIG-DDR3 controller

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Posted (edited)

Dear community,
I am a bit newbie in FPGA and Xilinx. I have a project that implementing a FIFO on Kintex 7. Because of some reasons, I have to use an external DDR3 to save data.
I found this tutorial on the Internet: http://xillybus.com/tutorials/deep-virtual-fifo-download-source (It connect 2 buffer standard FIFOs to a logic module, then connect to an external DDR3 via AXI4 MIG) and I modified it to match with my requirements by :
- Customizing DDR3 MIG IP(using MT4KTF25664HZ-1G9 - SODIMMs, AXI4 enabled).
- Adding 2 standard 512x16 FIFO IPs by FIFO Generator.
- Run synthesis and implementation properly.
My question is how to implement the simulation? Do I need a DDR3 model, connect it to MIG, then create a simple testbench for my FIFO?

Update: I found ddr3_model.v in MIG example module. I plan to use FIFO generator simulation module as my skeleton. However, FIFO generator vivado 2018.3 only generated vhd instead of verilog. How do I get verilog?
Thank you very much!
Best regards,
Charlie.

Edited by charlieho

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Hi @charlieho,

We have not worked with Xillylbus. Typically i set my project to verilog and then create a block design. From there interacting with ip blocks should not be an issue of verilog/vhdl. Is there a reason you need the FIFO Generator to be in Verilog? Verilog and VHDL modules/entities and IP's can interact together in the same project.    

best regards,

Jon

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Dear @jpeyron,

I need to implement a testbench to simulate our FIFO so I want to have FIFO generator simulation verilog code to modify.

Do you have any suggestion?

Thank you!

Charlie.

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Posted (edited)
On 7/5/2019 at 5:20 AM, charlieho said:

How do I get verilog?

In the Project Settings for the project in which you create your FIFO from the IP Wizard you can select VHDL or Verilog. In ISE there is a separate Core Generator file that does this for your IP. I have a few  tips:

  • You definitely need to use Verilog to simulate MIG code
  • You should avoid the AXI interface and just select the Native FIFO interface. This will be much easier to hook up to the Xillybus code. I've done a number of KC705 Xillybus project though without using the DDR for storage.
  • Start off by building the Xillybus project. After you think that you understand how his design works try creating a custom interface to provide some positive feedback on how well you do. After you are comfortable with the Xillybus then try an add the MIG DDR interface. There will be a lot of clocks involved and timing closure will start becoming tricky. If you try and jump to a final project it likely will take longer than if you progress through integrating interfaces in an orderly step by step manner. Having a verilog model for the DDR memory certainly helps with simulation.
  • After creating a MIG DDR interface it is not as simple as hooking up some FIFOs and reading data. You will need to create your own state machines to interact with your code and the DDR interface FIFOs to perform external read and write operations.

Regardless of any experience you might have developing FPGA DDR designs with other vendors devices and tools I suggest that you read through all of the relevant Xilinx literature. This includes IP documentation, Vivado simulation, etc. Jumping off a cliff into a pool is a lot safer if you know what's waiting for you once you hit the water....

Edited by zygot

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