Dear community,
I am a bit newbie in FPGA and Xilinx. I have a project that implementing a FIFO on Kintex 7. Because of some reasons, I have to use an external DDR3 to save data.
I found this tutorial on the Internet: http://xillybus.com/tutorials/deep-virtual-fifo-download-source (It connect 2 buffer standard FIFOs to a logic module, then connect to an external DDR3 via AXI4 MIG) and I modified it to match with my requirements by :
- Customizing DDR3 MIG IP(using MT4KTF25664HZ-1G9 - SODIMMs, AXI4 enabled).
- Adding 2 standard 512x16 FIFO IPs by FIFO Generator.
- Run synthesis and implementation properly.
My question is how to implement the simulation? Do I need a DDR3 model, connect it to MIG, then create a simple testbench for my FIFO?
Update: I found ddr3_model.v in MIG example module. I plan to use FIFO generator simulation module as my skeleton. However, FIFO generator vivado 2018.3 only generated vhd instead of verilog. How do I get verilog?
Thank you very much!
Best regards,
Charlie.
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charlieho
Dear community,
I am a bit newbie in FPGA and Xilinx. I have a project that implementing a FIFO on Kintex 7. Because of some reasons, I have to use an external DDR3 to save data.
I found this tutorial on the Internet: http://xillybus.com/tutorials/deep-virtual-fifo-download-source (It connect 2 buffer standard FIFOs to a logic module, then connect to an external DDR3 via AXI4 MIG) and I modified it to match with my requirements by :
- Customizing DDR3 MIG IP(using MT4KTF25664HZ-1G9 - SODIMMs, AXI4 enabled).
- Adding 2 standard 512x16 FIFO IPs by FIFO Generator.
- Run synthesis and implementation properly.
My question is how to implement the simulation? Do I need a DDR3 model, connect it to MIG, then create a simple testbench for my FIFO?
Update: I found ddr3_model.v in MIG example module. I plan to use FIFO generator simulation module as my skeleton. However, FIFO generator vivado 2018.3 only generated vhd instead of verilog. How do I get verilog?
Thank you very much!
Best regards,
Charlie.
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