Arty7_Lover Posted July 5, 2019 Share Posted July 5, 2019 I have synthesized zynq block well , but implementation removes bram. My picture is as follows. Implementation is made after runing block automation. Could you explain it? AXI_Traffic_Generator.srcs.zip Link to comment Share on other sites More sharing options...
D@n Posted July 5, 2019 Share Posted July 5, 2019 @Arty7_Lover, It might help if you shared more of what you were doing. How did you chose to configure this RAM that didn't show up? Dan Link to comment Share on other sites More sharing options...
Arty7_Lover Posted July 5, 2019 Author Share Posted July 5, 2019 single port RAM Link to comment Share on other sites More sharing options...
Arty7_Lover Posted July 5, 2019 Author Share Posted July 5, 2019 1 hour ago, D@n said: @Arty7_Lover, It might help if you shared more of what you were doing. How did you chose to configure this RAM that didn't show up? Dan Can Axi-lite connect with AXI4 slave bus directly? Link to comment Share on other sites More sharing options...
xc6lx45 Posted July 5, 2019 Share Posted July 5, 2019 check LUTs and FFs... implementation removes your whole design, more or less. For example, accidentally not driving a clock can cause this. Link to comment Share on other sites More sharing options...
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Arty7_Lover
I have synthesized zynq block well , but implementation removes bram.
My picture is as follows.
Implementation is made after runing block automation.
Could you explain it?
AXI_Traffic_Generator.srcs.zip
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Share on other sites
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