Higher frequency in the Aritx-7 FPGA layout

[Foisal Ahmed]

Hi,

I am using Xilinx Artix-7 FPGA  of device xc7a35ticpg236-1L. I made 7 stage ring oscillator using LUT-6 to observe the frequency of the various locations in the layout. The problem what I have found that the RO showing more higher frequency in the top row and bottom row of the layout than other row position. I have checked various position by row-wise. It is usual that all location has little difference to other adjacent position due to having some technological process variation.  But the difference between the top row of the layout and the adjacent row is around 10MHz. However, the usual difference is around 0.5-2 MHz. Thanks in advance for any comments and reasons.

Regards,

Foisal 

[xc6lx45]

I think you are operating far, far out of spec...

Just as a reality check: "process variations" in space need to be under control across the wafer for economic production. You're trying to show differences across the die. The old proverb applies, "correlation is not causality".

You might have a look at the delay budget in timing analysis for the paths. Probably you'll find your answers there.

And, I suspect with a few selected constraints for max. datapath delay (important: use -datapath_only flag) you can turn this result on its head...

 

[Foisal Ahmed]

Dear xc6lx45,

Thanks for your reply. Actually, my main concern is why the upper row and lower row in the layout showing significant higher frequency or lower delay than the adjacent row of the layout. I don't know actually whether the top row or bottom row of the layout is out of specification or not. So far, my designed ring oscillator meets the time specifications, as well. Looking for a more specific answer.

Please find the attachment file for the figures what I actually wanted to say.

Thanks,

Foisal

[xc6lx45]

BTW do you have several oscillators up at the same time, or only one? (risk of injection locking)

I think RC time constant charging is the most likely reason for the differences.

It may well be that the wires at the edge drive fewer (transmission) gates, less capacitive loading, smaller RC and thus faster. But who knows what micro-optimizations e.g. transistor size are involved (maybe also to save power). You might get an insight into what the tool knows if you check the predicted path delay between identical nodes in different rows. It'll also show the logic delay separately so you can check whether LUTs in different locations are known to the tool to have different speed.

 

[Foisal Ahmed]

@xc6lx45 Thanks again for the reply. At a time one oscillator is activated. What do you mean by injection locking?

[xc6lx45]

Nothing to worry about if only one is up at a time. It would mean that the frequencies of adjacent oscillators affect each other if they are running at the same time  ("injection pulling", to the point that they agree on a common frequency ("locking").

Consider the oscillator as an amplifier with a feedback loop. The feedback path plus phase shift lead to a fairly narrow frequency response around the oscillation frequency or harmonically related frequencies). Weird things can happen with the gain - while it is unity in average steady-state operation, the circuit can get highly sensitive to external interference that is (near)-correlated with the oscillator's own signal.

Wikipedia:

Perhaps the first to document these effects was Christiaan Huygens, the inventor of the pendulum clock, who was surprised to note that two pendulum clocks which normally would keep slightly different time nonetheless became perfectly synchronized when hung from a common beam