I am dealing with Vivado Ip cores. I want to design SPı interfaces by using AXI QUAD SPI in microblaze. Unfortunately, when I designed my cores and when I generated bitstream Imy designed failed. Also I added DDR3 because I tought that maybe Microblaze caches are not enough for SPI. Before the generating bitstream I get these critical warning in the validation session. When I ignore these warning as we know that my block designs failed. Can you help me this issue? I am really  dealing with with it . I would really appreciate it.




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Hi @jpeyron,

Yes I am using Arty A7 board I saw that you gave me the link which is getting started with microblaze but unfortunately I want to design Spi interface. My axi quad spi will work as a slave and I selected 1 master 1 slave and I added DDR3 but I got critical warning  also when I export these design to the SDK platfrom. I did not build my exist SPI code I got too many times .elf file error. So I am really dealing with SPI. Could you help me this issue especially about vivado part hardware design. 

Thanks for help.

Best Regards

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Hi @ozden.erdinc,

I would suggest using the Getting started with microblaze tutorial as a reference. On section 5 instead of adding the uart IP add the axi quad spi ip core.

Here is a forum thread that should help you get closer to getting slave mode working. I would also suggest to look through the AXI Quad SPI v3.2 LogiCORE IP Product Guide.

best regards,


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