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AXI DMA Minimal working example on Basys3

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I have been familiarizing myself with VHDL and FPGAs in general with the Digilent Basys3 board. Recently I have tried incorporating the Microblaze in to my design just to familiarize myself with it. I have created a simple block diagram where I connect a custom AXI-stream counter to an AXI-DMA block. The counter just streams incrementing numbers and adds the tlast signal to generate frames. My purpose is to develop a minimum working example on AXI-DMA transfer. I plan to transfer x-number of samples generated by the AXI-stream counter with the AXI-DMA to a BRAM memory. On programming the AXI-DMA core I have followed the Xilinx manual PG021 https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf section Direct Register Mode (Simple DMA) on page 71. Initializing the DMA works. However, after sending the transfer command to the DMA no transaction happens. I wonder whether the problem is in my C-code or the block diagram.

I have verified with the vivado ILA that the counter is working and produces a stream of data. In addition I have tied tkeep port to logical high on the s2mm port on the DMA. Is it possible I have forgotten something else? Any suggestions will be warmly welcomed.


Edited by Pertti56
Corrected a typo
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Hi @Pertti56,

Welcome to the Digilent Forums!

I am not seeing anything specifically.  Here is a pdf that might be helpful.

Have you been able to get the DMA examples here:  C:\Xilinx\SDK\2019.1\data\embeddedsw\XilinxProcessorIPLib\drivers\axidma_v9_9  work?

The most current documentation on the AXI DMA IP Core is available there as well.

best regards,


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