I follow the instruction to create the project, when I run synthesis, it just cannot stop in the procedure....
I got three warnings.
WARNING: [Vivado 12-4148] The synthesis checkpoint for IP 'C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/PxlClkGen/PxlClkGen.xci' is not generated and IP is locked, no out-of-context (OOC) run will be created. The synthesis may not be able to complete or could result in incorrect behavior.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [Vivado 12-4148] The synthesis checkpoint for IP 'C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/ClkGen/ClkGen.xci' is not generated and IP is locked, no out-of-context (OOC) run will be created. The synthesis may not be able to complete or could result in incorrect behavior.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products cant be done.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/ddr/ddr.xci
Question
wintermayr
Have anyone tried successfully to run the advanced I/O demo on nexys DDR ?
https://reference.digilentinc.com/nexys4-ddr:userdemo
I follow the instruction to create the project, when I run synthesis, it just cannot stop in the procedure....
I got three warnings.
WARNING: [Vivado 12-4148] The synthesis checkpoint for IP 'C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/PxlClkGen/PxlClkGen.xci' is not generated and IP is locked, no out-of-context (OOC) run will be created. The synthesis may not be able to complete or could result in incorrect behavior.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [Vivado 12-4148] The synthesis checkpoint for IP 'C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/ClkGen/ClkGen.xci' is not generated and IP is locked, no out-of-context (OOC) run will be created. The synthesis may not be able to complete or could result in incorrect behavior.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products cant be done.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/ddr/ddr.xci
Run output log is uploaded.
runme.log
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