Zybo is not able to boot up from QSPI Flash

[Ajeeth_kumar]

Hi, 
I am working on a project where i'm using Digilent zybo AP SoC with xilinx vivado for Hardware design and Xilinx SDK for software design.
My application uses following protocol/peripherals:
1. UARTns16550 PL side (Programmable Logic) in interrupt mode.
2. GPIOs
3. Ethernet mac (lwIP stack)

I started my software design using xilinx lwip perf client application project. Then i started modifying the perf client C code according to my need. 
My project contains Uartns16550, tcp/ip server and client program which receives real-time data.

So coming to my problem, i am able to run my application from xilinx sdk GDB and system debugger. But, when i dump my code in QSPI flash and try to boot, the zybo is not booting up.
I also tried loading different application project like tcp perf server, perf client. By doing this the processor boots up properly through QSPI flash. 
I followed the steps provided by Digilent for programming the flash and i also ensured that the jumpers are in the right place where it has to be. 
I believe that there's a problem with my program since i have started modifying the tcp perf client code for my project. I am not getting a clue where my code is going wrong.

Operating System : Windows 10
Software : Xilinx vivado 2018.3/SDK 2018.3

Any inputs related to this will be appreciated.

Thanks & Regards 
Ajeeth kumar 

 
 

[jpeyron]

Hi @Ajeeth_kumar,

If you are able please compress and attach your project or link to something like google drive or dropbox. 

Also add a delay into your project. The QSPI Flash might be trying to configure the FPGA before the power rails are stable. This thread had a similar issue.

best regards,

Jon

[Ajeeth_kumar]

Hi Jon,

Thanks for replying to my query,.

As you suggested, i have already tried adding some delay of 5 seconds in the beginning of my C program's main function.  I didn't find any difference by doing this activity.

I will share you the link to my project very shortly  

[Ajeeth_kumar]

Can i get your mail ID so that i can share the project to you personally.

[xc6lx45]

Hi,

shouldn't that delay go into the FSBL (not the user application)?

in fsbl_hooks.c there should be a function before bitstream upload, that seems a good place (or early in main.c)

 

[jpeyron]

Hi @Ajeeth_kumar,

@xc6lx45 is correct. You should be adding the delay in the FSBL so as to delay the project from trying to configure the FPGA. 

We would prefer using a file sharing site like Google Drive or Dropbox instead of work/personal emails.

best regards,

Jon

[Ajeeth_kumar]

Hi @xc6lx45,

Thanks for your suggestion.

I was trying to give a delay of 2 seconds  in the fsbl main function. still i didn't find any improvement with the delay. Kindly have a look at the attachments to know where exactly i add delay.

[Ajeeth_kumar]

Hi @jpeyron

Here is a link to my compressed Xilinx project --> https://drive.google.com/file/d/15HvUP4OmN7HSjwwvhAJ9DW-xC79KNIvr/view?usp=sharing

Regards

Ajeeth Kumar

[xc6lx45]

The first one in main() is correct.

The 2nd and 3rd one are after PL configuration.

Alternatively, locate this line

    fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n");

in fsbl_hooks.c and put it there but it should make no difference.

[Ajeeth_kumar]

Hi @xc6lx45  @jpeyron,

 

I have found out where exactly the problem lies in my project.

There's a problem in setting up of the interrupt for  UART (PL side). I have integrated 4 number of UART16550 IP, where  i have found that in interrupt setup only one UART16500 is setting up properly when it tries to initialize rest of the UART in software side the zybo hangs up. 

I guess i am not setting up the interrupt in a proper way.

My project has Ethernet and UART16550 which works interrupt based.

Below is my interrupt setup. 

interrupt_setup.c

[Ajeeth_kumar]

Hi @jpeyron @xc6lx45,

I'm glad to say that i have resolved the issue. The problem was in interrupt setup for UART, where i was calling send and receive function right after the initialization of each UART.

I would like to thank you for sparing your time in solving my issue.

Regards

Ajeeth kumar 

 

[jpeyron]

Hi @Ajeeth_kumar,

Glad to hear you were able find the issue and resolve it! Thank you for sharing what it was and how you fixed this issue.

best regards,

Jon