Genesys 2 FMC contraint file

[Saad1993]

Hi

I want to use a genesys2 FPGA with ADC from TI,so I download xdc file  of Genesys 2 from GitHub  to use FMC pin of Genesys 2  but I don't find the description of all pins especially those pins

[zygot]

The pins that your picture refers to are specific to the FMC Vita 57 standard. I suggest looking around the internet  for FMC pin name/functionality. More important is the pin name/functionality for the Xilinx FPGA device. Xilinx UG475 provides this information.

I'll warn you to make sure that you understand everything in the SelectIO and Clocking reference manuals if you intend to use IOSERDES. I've posted on this topic quite a lot and don't want to keep repeating myself.

Most Ti ADC/DAC serdes EVMs will be problematic on Xilinx boards. You have a decent chance using HSMC adapters and Altera boards. If you are prepared to make your own EVM/FMC adapter then you also have a good chance of success... as long as you understand all of the limitations involved with using IOSERDES and clocking pin assignments.

best of luck.

[Saad1993]

I want to use the JESD204B IP core, but my problem is  the  specification of IOSTANDARD of  each pin, like I know that IOSTANDARD is related to each FPGA and its not specified in the user guide of Xilinx.

 

[zygot]

I wasn't referring to IOSTARDARD when I was mentioning pin name/functionality. Everything that you need to know about IOSTANDARD capabilities of any IO pin is in Xilinx UG-471. Note that the Genesis2 uses the Kintex device and has both HP and HR IO banks. Digilent FMC equipped boards use a user settable Vadj voltage for FMC IO and this influences what possible IOSTANDARD you can opt to use.

Just read the Xilinx literature....

JESD204B is great but uses transceivers so... if you want to use those you need to read through UG-476 as well. I'm not aware of any Ti FMC ADC EVMs that target Xilinx FPGA boards. I'm assuming that you are making your own FMC mezzanine card. ??? I am also not aware of anyone offering JESD204B IP for free. Make sure that you know what you are doing as there are lot's of unhappy surprises for the uninformed and unprepared. The best chance of success is to choose a third party ADC FMC mezzanine board from a vendor that supplies some source code operability for a Xilinx board compatible with the Genesis2. Given the licensing issue you might find this advice hard to act on.

[edit]

Analog Devices offers JESD204B ADC devices and a few FMC cards with them. They generally have some good FPGA support but good luck trying to change their demo source to fit a custom application. You might want to snoop around the ADI website. Caution!!! The devil is in the details.. and the vital details are usually hard to come by without a lot of work. Pin assignments by FPGA board vendors can break a project so expect to spend some time tracking down each pin on the schematic for compatibility. Been there, done that on a few occasions. MAKE NO ASSUMPTIONS!!!

[zygot]

Perhaps I misunderstood your question. Since Digilent doesn't make any FMC mezzanine boards using the transceivers their basic constraints file ignores these pins. One possibility is to look at one of the ADI FMC 204B project files and see what they use for IOSTANDARD property values. ADI does target the KC705 and the Genesys2 heavily borrows from that design. I don't know if there even is a Kintex transceiver Application Note for transceivers as neither Intel or Xilinx is particularly interested in help users use transceivers for any but the high end devices.

Perhaps the @elodgDigilent engineer who characterised and tested the Genesis2 FMC transceivers has some information. I don't believe that the transceiver pins support any IOSTANDARD but are dedicated for use as transceiver IO.

[elodg]

This seems relevant:

The same goes for GTX transceivers on the G2. Either use the wizard for your IP and do the lane mapping there, or instantiate it as GTX primitives and write a LOC constraint for the channel primitive. Since the channel primitive is fixed to its pins and there is no IOSTANDARD to specify, you do not need to constrain the pins at all.

This is what I see in the JESD wizard.