Question

Hi ,

I didn't find the dedicated libraries for PMOD CLP IP core in Vivado library for Pmods !

Kindly, if someone have an experience with it , I hope from you to instruct me about how to use it.

Thanks. 

 

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Hi @Ahmed Alfadhel,

We have not had the bandwidth to create an IP Core for the Pmod CLP. We have verilog and VHDL ISE projects that can be alter to work with vivado on the Pmod CLS resource center . You will need to use the UCF file as a reference for the XDC file.

You should be able to use the ADD a Module function in the Vivado Block design as discusses in this forum as well as in this xilinx YouTube to use these projects with Microblaze. 

You can use the add a module function as described in this Xilinx YouTube. The add a module function allow users access to the AXI bus with their VHDL Entities/Verilog Modules.  Here is a forum thread that discusses this as well.

best regards,

Jon

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