Output Port on IP Core

[newkid_old]

I created a custom IP block that has some inputs and an output.  I've ran the logic through the simulator and confirmed that everything is working as expected.  I've packaged the custom block and added to the Arty A7 board.  I've tied the output of my module to an physical output of the Arty (PMOD A pint to be precise).  My problem is that I get no output from my module.  I look at the signal with my oscope and see what looks to be a 80mV pulse where there should be a 3.3v pulse.  Any help or clue as to why I'm not seeing my output would greatly be appreciated?

 

Cheers

[jpeyron]

Hi @newkid_old,

I would suggest using the ILA module. Here is a Xilinx forum that discusses this.  Here is the Integrated Logic Analyzer v6.2 LogiCORE IP Product Guide that should also be helpful.

Best regards,

Jon

 

[newkid_old]

Jon,

   Thanks for the pointer on the ILA.  Whereas I wasn't able to get the module running in my block design I was able to find my problem.  The simulation ran fine for my IP but when I tried the Implemented Simulator, I'm seeing exactly what I see on my o-scope which is a 12nS pulse.  I have no experience in troubleshooting between simulator and implemented design.  Any suggestions?

 

Cheers

[jpeyron]

Hi @newkid_old,

 I would suggest simulating the whole project to find where the issues are or adding the ILA module to view specific signals of interest.

best regards,

Jon  

[newkid_old]

I found a solution to this issue but not using the ILA module.  I found this setting in the Synthesis tab in the settings called "keep equivalent registers".  Clicked this setting and rerun the synthesis.  It was deleting my Pulse_Length(15:0) input for some reason and this setting keeps it.  Hopefully this bit of knowledge will help someone.

 

Cheers,

Curt

[xc6lx45]

Hi,

check the warnings. Most likely there is a bug in your design. If the tools remove logic, it's redundant - either you did tie it intentionally to a constant or there is some other issue (e.g. no clock) that makes the pulse_length input non-observable in the output.

You might add a final output register right before the IO interface with the DONT_TOUCH attribute: The tools will deliver an implementation that is "correct" as seen by static timing-analysis (setup, hold margins etc). The signal is free to do whatever between clock edges (see "hazards" on Wikipedia). But I suspect this is not the main issue here if parts get optimized away.

 

[D@n]

@newkid_old,

Are you registering your output pulse before it leaves the chip, or is it still driven by some combinatorial logic?  There are some types of simulation synthesis mismatch issues that can be solved by registering all I/O's.

Dan

[newkid_old]

If there is errors, I didn't see any and I do have my module running on an Art A7 board.  I do register my Pulse_Out with the clock event  in an IF statement.  Here is my code:

I changed the Pulse_Count to 8 bits which is different from the block seen above that's 16 bit.  Any pointers are appreciated.

entity Pulse_Trigger is
    Port ( Reset : in STD_LOGIC;
           Clk : in std_logic;
           Trigger : in std_logic;
           Pulse_Length : in STD_LOGIC_VECTOR (7 downto 0);
           Pulse : out STD_LOGIC);
end Pulse_Trigger;

architecture Behavioral of Pulse_Trigger is
signal count    : std_logic_vector(7 downto 0);
signal pulseon  : std_logic;
signal pulsetrig: std_logic;
begin
    process(Reset, Clk, Trigger)
        begin
            if Reset = '1' then --reset logic
                Pulse <= '0';
                pulseon <= '0';
                pulsetrig <= '1';
                count <= Pulse_Length;  --load the current count into
            else
                if(Clk'event and Clk = '1' and Trigger = '1' and pulseon = '0' and pulsetrig = '1')then --Once the trigger pulse goes high latch
                    pulseon <= '1'; --buffer that mirrors the output
                    Pulse <= '1';   --fire the pulse
                    
                    pulsetrig <= '0';
                end if;
                if(Clk'event and Clk = '1' and pulseon = '1')then
                    count <= unsigned(count) - '1';
                end if;
                if(count = "00000000" and pulseon = '1')then
                    Pulse <= '0';   --fire the pulse
                    pulseon <= '0'; --buffer that mirrors the output
                    
                end if;
                if(pulseon = '0' and Trigger = '0' and pulsetrig = '0')then --The pulse length has timed and the trigger has gone low
                    pulsetrig <= '1';
                end if;
                
            end if;
    end process;
end Behavioral;

 

[xc6lx45]

>> if(count = "00000000" and pulseon = '1')then

>> if(pulseon = '0' and Trigger = '0' and pulsetrig = '0')then

shouldn't there be Clk'event in this?

Without good reason, I would strictly avoid any non-clocked code e.g. reset That is,

if(Clk'event and Clk = '1') then

... all your code here