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cfsterpka

Propper usage of XADC output channel signal?

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Posted (edited)

I'm attempting to use all 6 single ended ADC channels of the PYNQ-Z1 board with DRP enabled and with continuous sequencing (see attached configuration).  According to the 7-series XADC guide UG480 on page 72, "When XADC is being operated in a sequence mode, you can identify the channel being converted by monitoring the channel address (CHANNEL[4:0]) logic outputs. The multiplexer channel address of the channel being converted is updated on these logic outputs when BUSY transitions Low at the end of the conversion phase."   But the output of the channel (channel_out) is always zero, which I've worked around by outputting the previously selected channel with the data on the EOS signal.  The issue is that it seems some of my samples are being labeled incorrectly, for example with a 500Hz signal on A4 and a constant 0.23V on A2 this is what I get:

 112421574_Screenshotfrom2019-06-1912-22-38.png.a7e884bb313dd7d58b3de1c4f47ee479.png

 

As you can see, it looks like some of the sinusoidal signal is being labeled as A2 and some of the DC is being labeled as A4.  It would be much easier to debug what was going on if I could just read the channel_out signal with the conversion on EOS, but for whatever reason it always reads zero when I connect a wire to channel_out.  Is there anything else I have to configure to get this to work correctly?

 

Thanks,

Chris

 

xadc_wiz_0.v

Edited by cfsterpka

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Hi @cfsterpka,

Here is an Arty-Z7-20 project that should work for the PYNQ-Z1.  Here on page 9 of  schematic bank 35 for the PYNQ-Z1 it show which XADC channels are accessible. 

best regards,

Jon

 

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Thanks @jpeyron,

 

Ah okay - I think I see what's going on.  I attached the EOS signal to data_out on the example design and it looks like EOS going high does not correspond well with when channel_out is active.  Is this the expected behaviour?  The way I was reading the diagrams in UG480 on pages 72 and 75 is that the channel out would only be indeterminate briefly on the first cycle of the ADCCLK (e.g. immediately after busy goes low).   Based on the example design I'm guessing the best time to grab the channel out would be on the drdy_out signal, does that make sense?

 

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Hi @cfsterpka,

You are correct the drdy_out signal tell us when data is ready to be read from the XADC. In the XADCdemo.v for the Arty-Z7-20 xadc project the wire ready is the output signal from the xadc wizard:

 

wire ready;  //XADC port that declares when data is ready to be taken

 

xadc_wiz_0 XLXI_7 (

.daddr_in (Address_in),

.dclk_in (clk),

.den_in (enable & |sw),

.di_in (),

.dwe_in (),

.busy_out (),

.vauxp12 (xa_p[0]),

.vauxn12 (xa_n[0]),

.vauxp0 (xa_p[1]),

.vauxn0 (xa_n[1]),

.do_out (data),

.eoc_out (enable),

.channel_out (channel_out),

.drdy_out (ready)

);

best regards,

Jon

 

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Posted (edited)

Thanks @jpeyron

I'm still having a bit of difficulty reading the output of the channel_out port correctly.  I can see channel_out working correctly in the example code, but I have a custom AXI streaming IP that is managing the XADC but the method I am using always outputs zero.  I'm not sure what I am doing wrong, since I am still using the ready signal as a trigger for saving the channel out to a register.  For reference, this is how I am managing the  XADC and channel out:

 

    //data & logic enable strobe generation
   always@(posedge clk)
       fork
          last_ready <= ready;
       join
    assign ready_pe_strobe = (last_ready == 1'b0 && ready == 1'b1) ? 1'b1 : 1'b0;
    assign ready_ne_strobe = (last_ready == 1'b1 && ready == 1'b0) ? 1'b1 : 1'b0;

reg [4:0] och;

reg [31:0] ofval;

 

always @(posedge clk)
begin

if (ready_pe_strobe) och <= channel_out;

if(EOS)
  begin

if(Address_in == 7'h11) //A0: Tmon
     fork
      ADCsig = 3'b000;
      ofval <= {och,ADCsig,data};   
      datavalid <= 1'b1;
     join  
    if(Address_in == 7'h19) //A1: HVmon
      fork
       //Address_in=7'h19;
       ADCsig = 3'b001; //A1: HVmon
       ofval <= {och,ADCsig,data};   
       datavalid <= 1'b1;      
      join

     ...

     ... continues for 4 more channels

    end

end

 

best,

Chris

Edited by cfsterpka

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I found a useful hint.  When I assign my output port (to the AXIs bus) directly to och and och is updated on clk (100MHz) I can see the channel_out change.

e.g.

always@(posedge clk)

   begin

    och <= channel_out;

   end

assign out_to_axis = och;

 

but in the code in the previous post "out_to_axis" is assigned ofval.  Interesting.

 

 

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Hi @cfsterpka,

I would suggest to simulate the project. This might be a helpful thread for simulating the xadc. Another option would be to add a ILA module so to view specific signals.

best regards,

Jon

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