Arty - Axi ethernet lite VHDL

[rakeshm55]

Hi,

I have an Arty board with me.

I would like to control the ethernet port using AXI ethernet lite . I want to use VHDL to control Axi interface of ethernet mac. 

I am not looking for tcp/ip or udp over the port. I will be using it to experiment with mac to mac data exchange. I would like to start by sending packets and capture it using  wireshark.

Later will use this interface to exchange data with a processor board using raw socket communication. MAC ids are known in prior.

Do you have any VHDL example for controlling axi lite/ axi ethernet lite.?? How to emulate the axi master behaviour?? I guess there is a VHDL example for axi etherent in vivado. as i understand the axi commands were generated using ATG.

Is there any sample design or design guide on how to proceed?? I would like to know where to start from.

 

 

 

[jpeyron]

Hi @rakeshm55,

Sounds like an interesting project.  We have not had the bandwidth to facilitate the AXI bus interface through HDL.  Here is  a project that could be a good reference.  Here is a Arty VHDL ethernet project done by a community member @hamster that should be helpful.

best regards,

Jon

[rakeshm55]

Does that mean that it's hard to control axi lite interface using vhdl?.... Is there any implementation available for axi master??.... 

[jpeyron]

Hi @rakeshm55,

Unfortunately, we do not have an HDL Controller for any of the AXI bus types.  I have not found any with a quick internet search. Here, Here and here are forum threads that discuss the AXI bus along with the wishbone bus which might be helpful. 

best regards,

Jon