Implementation Error when using two sepatate MIG instances and leaving one disconnected on Nexys 4 DDR

[dmishins]

Hi,

I'm trying to create a project that uses custom HDL code to write to the DDR2 memory on my nexys 4 ddr, and then ultimately uses microblaze to read the memory out over UART.

As an intermediate step, I created a vhdl "wrapper" to connect microblaze to ram and instantiate my custom vhdl.  At first I want to leave the signals from the custom VHDL that go to ram open/disconnected.  My plan was to later add a conditional logic statement that decides which is connected.

When I try to leave the pins to memory "open", or even connected to junk placeholder signals I created, I get an implementation error:

Quote

[Place 30-99] Placer failed with error: 'There are more instances than sites for type XADC'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

This doesn't make any sense to me, especially as I am not trying to use the XADC anywhere in the project.

I saw this article about leaving pins open, but I believe I followed the solution they have listed but still get the error.

I've attached the project folder for this in case anyone may be able to take a look. Since the file is too large to attach, it is at this google drive link.

Thank you,

Daniel

 

[kwilber]

This link explains why the xadc is being included when you use the mig. https://www.xilinx.com/support/answers/51687.html

[dmishins]

Ah, thank you @kwilber. That explains why the XADC error shows up at all, but I'm guessing that the XADC part may be a red herring on what is actually going wrong?  I seem to get this error even when I completely disable the MIG ip core that I use in my custom VHDL code, but the error goes away when I comment out the port map for either my custom code or microblaze completely.

[dmishins]

I've made some progress on this since I last posted.  I based my original custom logic design on the OOB user demo which had a component to read the temperature from the XADC to give to the MIG.  When I deleted that block (and therefore, had to delete the MIG) I was able to get things to work.

 

My new confusion moving forward is getting both the custom vhdl and the micoblaze to talk to the DDR2 at the same time.  Right now I have two separate MIG instantiations, but whenever I try to leave both instantiations uncommented (but even when I leave the pins of one connected to "open") I get tons of errors.  I of course expect some issues because I removed the connection to the XADC temperature sensor and just set MIG input for temperature to a fixed value as a test.  However, I can't seem to get the code to implement.

My question is, should I now try to debug my errors in the instantiation, or should I try to redesign only using one MIG block and changing which interface (microblaze or custom vldl) connects to it?  Is it even possible to have two MIG blocks for the same chip in a project?

Thanks,

Daniel

 

EDIT: It seems like I am going to need two separate MIG instances because the one that should talk to microblaze needs an AXI interface while the one I use for VHDL has a normal interface. Any suggestions on how I might do that?

[jpeyron]

Hi @dmishins,

You can use the add a module function as described in this Xilinx YouTube. The add a module function allow users access to the AXI bus with their VHDL Entities/Verilog Modules.  Here is a forum thread that discusses this as well.

Please attach a screen shot of your Block design if possible.

best regards,

Jon