Measure Clock on Arty

[PoojaN]

I am currently working on Arty A7 board and I want to measure my clock using a scope. Is there any way I can map the clock to any of the I/O pins?

I tried using command 

set_property CLOCK_DEDICATED_ROUTEFALSE[ G13 CLK_IBUF ], but I the following error while programming the board with the bitstream,

ERROR: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device.

Is there any way I can do this? Any help regarding clocks would be appreciated.

 

[jpeyron]

Hi @PoojaN,

Here is project I made in Vivado 2017.4 using the ODDR IP Core. I made two ports by right clicking on the block design. Both are type clock and one direction is input at 100 MHz and the other direction is an output. I connected the appropriate pins from the ODDR to the ports. I then created a wrapper. With the wrapper information I added a xdc using using the pin names in the wrapper. I then generated a bitstream. Next I opened the Hardware Manager and configured the Arty A7 with the bitstream. I then probed the pin 1 on JA (the pin I used for this project) with the Analog Discovery 2. It is showing a 400 KHz signal.  I have included screen shots of the process.

best regards,

Jon

[hamster]

Hi!

What you want to do is to create a DDR Output primitive , set the outputs to "0" and "1", and then connect the clock to the DDR Register's clock.

It's called "clock forwarding" and it is a pretty standard technique to make a clock visible to the outside world.

Oh, and I think you might have the wrong FPGA selected in your project settings. That is want is causing the "Bitfile is incompatible" error.

 

....
Library UNISIM;
use UNISIM.vcomponents.all;
....
ODDR1 : ODDR  generic map(DDR_CLK_EDGE => "SAME_EDGE",  INIT => '0', SRTYPE => "SYNC") 
             port map (Q => output_pin, C => clk100, CE => '1', D1 => '0', '1', R => '0', S => '0');
....

 

[PoojaN]

Hi! @hamster

Thank you for the answer, but could you please tell me how to ODDR output? I am pretty new to this. Also I am using Arty A7, which has Artix-7 FPGA, and all the information I could get was limited till Spartan-6 FPGAs.

Thank You! 

[jpeyron]

Hi @PoojaN,

Here is a xilinx forum that should help you with using the ODDR with the Arty-A7.

best regards,

Jon

[PoojaN]

Hii @jpeyron

I followed the same tutorial, but I am not able to understand where to specify my output pin where I will be able to scope my clock. 

[PoojaN]

5 hours ago, jpeyron said:

Hi @PoojaN,

Here is project I made in Vivado 2017.4 using the ODDR IP Core. I made two ports by right clicking on the block design. Both are type clock and one direction is input at 100 MHz and the other direction is an output. I connected the appropriate pins from the ODDR to the ports. I then created a wrapper. With the wrapper information I added a xdc using using the pin names in the wrapper. I then generated a bitstream. Next I opened the Hardware Manager and configured the Arty A7 with the bitstream. I then probed the pin 1 on JA (the pin I used for this project) with the Analog Discovery 2. It is showing a 400 KHz signal.  I have included screen shots of the process.

best regards,

Jon

Hi @jpeyron

Thank you for the answer. I was able to map the clock to the JA1 port using the ODDR, however the port was out of phase and I wanted to buffer this output as I want to interface the outputs of Arty with another chip set. 

This is the output that I observed on the scope.

The yellow trace is the on board oscillator and the blue trace is the output through the ODDR.  

And just out of curiosity, was your Discovery 2 in scope mode or logic analyzer mode?

[jpeyron]

Hi @PoojaN

i was using the logic analyzer mode. 

best regards,

Jon