Arty A7 - Bootloader does not load

[TomF]

Hello,

I am currently working on a Project involving a Microblaze core on an Arty A7 board. Everything works fine by programming the board nonpermantly from Vivado and SDK. I am using 2018.3 and even tried 2019.1 today.

However, there is a problem with the startup of the firmware, when I upload it to the flash memory following the "How To Store Your SDK Project in SPI Flash" tutorial.

First of all, when I power the device, the FPGA is initialized which I can see by an LED lighting up as it is hardwired to a constant 1. "Done" LED also lights up. The problem is, that the bootloader does not load anything. When I debug the bootloader by printing something over  UART (verbose mode), there is nothing. When I run the system debugger from SDK with the bootloader code, the bootloader starts and sucessfully reads the flash from Address 0xC00000 and my application starts on the microblaze. 

What am I doing wrong and what can I do to find the problem?

 

Best regards

[jpeyron]

Hi @TomF,

I would suggest to start with a fresh project.

Here is an older tutorial that should help you get a basic microblaze project going.

When the tutorial has you add the uart lite ip core add the QSPI flash ip. Add an additional 50 MHz clock on the clocking wizard and connect it to the ext_spi_clk on the qspi flash ip core. 

In project setting in bitstream select .bin then run implementation. When it is finished open the implementation.

Then follow the How To Store Your SDK Project in SPI Flash tutorial.

best regards,

Jon 

[jpeyron]

Hi @TomF,

Are you using the Digilent boards files?

When doing block automation in vivado I would suggest using 32KB for local and 16 KB for cache. 

Please attach a screen shot of your block design.

What frequency are you giving the ext_spi_clk on the QSPI Flash IP Core?

best regards,

Jon

[TomF]

Hi jpeyron,

 

thank you for your reply. The digilent board files are installed and I used the board macro to initialize the qspi for the flash. I have chosen 16kb for Cache and 32bkb local memory, as described in "Getting started with microblaze servers".

I am using the same clock for ext_spi_clk as for the AXI (s_axi_aclk) which is the same for all AXI blocks running on 83.333MHz. I also tried a separate clock from clk_wiiz with 66.333MHz which didn't work either.

Please see attached my block diagram. On the lower left there is other logic concerning the PL and some AXI GPIO connecting to it.

 

 

[jpeyron]

Hi @TomF,

Here is completed and verified Arty A7 QSPI Vivado 2018.2 project. 

What frequency are you giving the ext_spi_clk pin on the QSPI Flash IP Core?

best regards,

Jon

[TomF]

In case of the same as AXI clock it is 83.33 MHz, on separate clock it is 66.66Mhz.

I will try your example now

[TomF]

Your example works fine on my hardware. The only things that I was able to find to be different from my design is the bitstream settings. They are also different from the avnet manual: https://www.avnet.com/opasdata/d120001/medias/docus/178/UG-AES-A7MB-7A35T-G_Arty_OOB_GPIO_demo_V1.pdf

After adjusting the bitstream settings to be the same as yours, Vivado throws an error message: "invalid stof argument". 

I am stuck at this point

[TomF]

Hi @jpeyron,

I got it working now by creating a fresh project. I will now move on to port my previous PL to the new project and shold get everything running.

Thank you for your help!