PMOD AD1 Vcc Changes How Device Behaves

[tmwhitt]

Hello,

I have a PMOD AD1 that I am driving with a CMOD A7 board, and I am using some Verilog to drive the CS and SCLK pins. When I use a 5V Vcc source, the SDATA pin behaves exactly as I would expect as I vary the input voltage (an increasing binary signal). However, when I use a Vcc of 3.3V, I found that the SDATA pin is high for all SCLK cycles after about the 6th cycle. Also, I do not get out the expected four zeros on the first four SCLK cycles. The spec sheet for the AD7476A says I should be able to use a Vcc of down to 2.5V, so I was wondering if I am doing something wrong here? I tried using an external power supply to see if I wasn't supplying enough current, however it resulted in the same results.

Any help or suggestions are appreciated!

[JColvin]

Hi @tmwhitt,

What voltage range are you applying the inputs on the Pmod AD1?

Thank you,
JColvin

[jpeyron]

Hi @tmwhitt,

Welcome to the Digilent forums!

To add to @JColvin's post I would suggest looking at a community members ( @hamster ) project here. It is a completed VHDL project that should help with your Verilog project.

Are you trying to use both channels? 

We also have an Pmod AD1 IP Core here found in the Vivado library here . The Getting Started with Digilent Pmod IPs tutorial should be helpful with using the Pmod AD1 IP Core.

best regards,

Jon

[tmwhitt]

Thank you for the responses!

 

@JColvin, I am applying from 0-1V to the A0 pin, the signal is just a DC voltage.

@jpeyron, currently I am only trying to use one channel in. If I use a 5V Vcc and use two resistors to drop D0 (or SDATA) down to ~3.1V, the Verilog code I have works to read in the values. My issue is when 3.3V is applied, the device doesn't behave as expected.

I have attached three images, where the white trace is SCLK, the yellow trace is CS, and the green trace is SDATA. One is using the 5V Vdd, which shows it behaving as expected as I adjust the input voltage. The other two images are with a 3.3V Vdd, where they are at two different input voltages.

I do notice that when 3.3V is supplied, sdata is sometimes a 1 during the first couple cycles when it should only be zeros, which is odd to me.

Thanks again!

[tmwhitt]

Whoops, the files were too large and didn't attach correctly, here are the compressed versions of the images.

[tmwhitt]

The top two are using a 3.3V Vcc, the bottom one is with a 5V Vcc

[jpeyron]

Hi @tmwhitt,

To verify the Pmod AD1 is correctly working please use the Pmod DA1 IP Core with the Pmod Port JA using tutorial link above.

Using the Pmod Ad1 IP Core are you getting expected results?  

Also please attach a picture of you physical set up and Verilog code as well if possible. 

best regards,

Jon