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Nexys4 DDR- USB-UART Bridge (J6)


I designed a project in the Xilinx blocks then convert it to Vivado 2017.4 as IP, The problem is, i cant make synchronization between TX and RX by using the two FPGA Nexys4 DDR, Can I use the USB-UART Bridge (J6) to solve this problem? Note that neither microblaze nor the axi is used

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