zybo image processing

[lokender]

 

Hello to all,

i have start working on video processing through zybo board,so for that i have gone to digilent zybo video workshop file, its link is provided below

http://web-pcm.cnfm.fr/wp-content/uploads/2017/04/Workbook-Digilent_ZYBO_Video_Workshop.pdf

i gone through all steps carefully make all connection as shown in file but still nothing show 

Changes i have done in ip

clocking wizard ip : sys_clock take 125mhz freq and set to mmcm at 200 mhz output

dvi2rgb1v_7 ip : preferred resolution 1280*720 and other option as guided in file

and other ip changes as provided in file

Regarding error: their is no error or any critical warning is shown in vivado 2016.2 version

bur still nothing shows,even though i have provided external power supply 5v to it and change jumper to its  specific part  

edge detetion works fine and show rover output so i imported it in design and the complete design image i add in attachment.( i have twice check the hdmi cable ,vga projector and lp output all works fine) 

 

There is one warning generated in vivado after bitstream generation:

WARNING: [xilinx.com:ip:v_axi4s_vid_out:4.0-307] /v_axi4s_vid_out_0 video_in-TDATA: Bus sub-field mismatch. /v_axi4s_vid_out_0 field count: 3. /edge_detect_0 stream_out-TDATA field count: 1.

 

pls provide some solution or any other help  ASAP

 

[jpeyron]

Hi @lokender,

Welcome for the Digilent Forums!

I am not seeing anything specifically wrong with your project.

After generating the initial working project, i would suggest only altering one part of your desired changes so as to better trouble shoot the issues. I would also suggest using the the vivado library from here. 

Makes sure to be looking through the documentation provided in the vivado library for the IP Cores that are being used in this project.

Here is a Hackster.io project that might be helpful  as well.

best regards,

Jon

[lokender]

Hi jpeyron,

I had downloaded the vivado library from the above directory but when i use the dvi2rgb ip in the block design, for making hdmi input connection i clicked on ctrl+t but no external pin is generated  i am attaching the screenshot . 

Secondly i had run the video pipeline on the zybo board without the edge_detect ip with my previous design and output was coming same as input on the monitor through vga cable. But after inserting the edge_detect block there is no output coming on monitor through vga . i had tried the steps given by you .  Kindly look into it and provide me the possible solution . I had tried most of the permutations still not getting the output. 

For my previous design when i connect edge_detect block there is one warning generated in vivado after bitstream generation:

WARNING: [xilinx.com:ip:v_axi4s_vid_out:4.0-307] /v_axi4s_vid_out_0 video_in-TDATA: Bus sub-field mismatch. /v_axi4s_vid_out_0 field count: 3. /edge_detect_0 stream_out-TDATA field count: 1.

 

Kindly help asap .

my email id is - lokendervashist2@gmail.com

[lokender]

Hi jpeyron,

If you have a video processing project having sobel edge detection block made in vivado 2016.2 for zybo z7010 board kindly mail it .

my email id is - lokendervashist2@gmail.com

 

Thanks

Lokender

[lokender]

Hi jpeyron,

When i add edge_detect block generated in vivado HLS in the working vedio processing piepline there is one warning generated . please have a closer look and tell me what could be the reason behind it and whether it is causing any hindrance and what are the possible solutions.

 

WARNING: [xilinx.com:ip:v_axi4s_vid_out:4.0-307] /v_axi4s_vid_out_0 video_in-TDATA: Bus sub-field mismatch. /v_axi4s_vid_out_0 field count: 3. /edge_detect_0 stream_out-TDATA field count: 1.

kindly replay asap 

Thanks

Lokender

[jpeyron]

Hi @lokender,

I believe this is stating that the bus width is different from the axi4 vid out and the stream_out-TDATA field. Here is a xilinx forum thread where they had a similar issue. Here is the Zybo resource center. Here is our SDSoC projects which has a sobel filter project for the Zybo but it is done in Vivado 2015.4.

best regards,

Jon

[sumeet]

hii @lokender

did you solve the issue?. I am also facing similar issue. If solved could you please post the solution.

 

Thankx